Datasheet ADP2105, ADP2106, ADP2107 (Analog Devices) - 8

ManufacturerAnalog Devices
Description2 Amp Synchronous, Step-Down DC-to-DC Converter
Pages / Page36 / 8 — ADP2105/ADP2106/ADP2107. Data Sheet. PIN CONFIGURATION AND FUNCTION …
RevisionE
File Format / SizePDF / 1.0 Mb
Document LanguageEnglish

ADP2105/ADP2106/ADP2107. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. IN1. EN 1. 12 LX2. GND 2. 11 PGND. ADP2105/ ADP2106/

ADP2105/ADP2106/ADP2107 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN1 EN 1 12 LX2 GND 2 11 PGND ADP2105/ ADP2106/

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ADP2105/ADP2106/ADP2107 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN1 ND W FB G IN P 16 15 14 13 EN 1 12 LX2 GND 2 11 PGND ADP2105/ ADP2106/ GND 3 10 LX1 ADP2107 GND 4 9 PWIN2 TOP VIEW 5 6 7 8 P M SS ND NC CO AG NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD SHOULD BE SOLDERED TO AN
003
EXTERNAL GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION.
06079- Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 EN Enable Input. Drive EN high to turn on the device. Drive EN low to turn off the device and reduce the input current to 0.1 µA. 2, 3, 4, 15 GND Test Pins. These pins are used for internal testing and are not ground return pins. These pins are to be tied to the AGND plane as close as possible to the ADP2105/ADP2106/ADP2107. 5 COMP Feedback Loop Compensation Node. COMP is the output of the internal transconductance error amplifier. Place a series RC network from COMP to AGND to compensate the converter. See the Loop Compensation section. 6 SS Soft Start Input. Place a capacitor from SS to AGND to set the soft start period. A 1 nF capacitor sets a 1 ms soft start period. 7 AGND Analog Ground. Connect the ground of the compensation components, the soft start capacitor, and the voltage divider on the FB pin to the AGND pin as close as possible to the ADP2105/ ADP2106/ADP2107. The AGND is also to be connected to the exposed pad of ADP2105/ADP2106/ADP2107. 8 NC No Connect. This is not internally connected and can be connected to other pins or left unconnected. 9, 13 PWIN2, Power Source Inputs. The source of the PFET high-side switch. Bypass each PWIN pin to the nearest PGND plane with a PWIN1 4.7 µF or greater capacitor as close as possible to the ADP2105/ADP2106/ ADP2107. See the Input Capacitor Selection section. 10, 12 LX1, LX2 Switch Outputs. The drain of the P-channel power switch and N-channel synchronous rectifier. These pins are to be tied together and connected to the output LC filter between LX and the output voltage. 11 PGND Power Ground. Connect the ground return of all input and output capacitors to the PGND pin using a power ground plane as close as possible to the ADP2105/ADP2106/ADP2107. The PGND is then to be connected to the exposed pad of the ADP2105/ADP2106/ADP2107. 14 IN Power Input. The power source for the ADP2105/ADP2106/ADP2107 internal circuitry. Connect IN and PWIN1 with a 10 Ω resistor as close as possible to the ADP2105/ADP2106/ADP2107. Bypass IN to AGND with a 0.1 µF or greater capacitor. See the Input Filter section. 16 FB Output Voltage Sense or Feedback Input. For fixed output versions, connect to the output voltage. For adjustable versions, FB is the input to the error amplifier. Drive FB through a resistive voltage divider to set the output voltage. The FB regulation voltage is 0.8 V. EP Exposed Pad. The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation. Rev. E | Page 8 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL OPERATING CIRCUIT REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE BOUNDARY CONDITION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL SCHEME PWM MODE OPERATION PFM MODE OPERATION PULSE-SKIPPING THRESHOLD 100% DUTY CYCLE OPERATION (LDO MODE) DESIGN FEATURES Enable/Shutdown Synchronous Rectification Current Limit Short-Circuit Protection Undervoltage Lockout (UVLO) Thermal Protection Soft Start APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL EXTERNAL COMPONENT SELECTION SETTING THE OUTPUT VOLTAGE INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION INPUT FILTER SOFT START PERIOD LOOP COMPENSATION BODE PLOTS LOAD TRANSIENT RESPONSE EFFICIENCY CONSIDERATIONS Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses THERMAL CONSIDERATIONS DESIGN EXAMPLE EXTERNAL COMPONENT RECOMMENDATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS EVALUATION BOARD EVALUATION BOARD SCHEMATIC FOR ADP2107 (1.8 V) RECOMMENDED PCB LAYOUT (EVALUATION BOARD LAYOUT) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE