Datasheet LTC3406B-1.2 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 1.5MHz, 600mA Synchronous Step-Down Regulator in ThinSOT |
| Pages / Page | 12 / 10 — APPLICATIO S I FOR ATIO. Design Example. PC Board Layout Checklist. … |
| File Format / Size | PDF / 276 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Design Example. PC Board Layout Checklist. Figure 3. LTC3406B-1.2 Layout Diagram
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Text Version of Document
LTC3406B-1.2
U U W U APPLICATIO S I FOR ATIO
The regulator loop then acts to return VOUT to its steady- 3. Keep the (–) plates of CIN and COUT as close as possible. state value. During this recovery time VOUT can be moni- tored for overshoot or ringing that would indicate a stability
Design Example
problem. For a detailed explanation of switching control As a design example, assume the LTC3406B-1.2 is used loop theory, see Application Note 76. in a single lithium-ion battery-powered cellular phone A second, more severe transient is caused by switching in application. The VIN will be operating from a maximum of loads with large (>1µF) supply bypass capacitors. The 4.2V down to about 2.7V. The load current requirement discharged bypass capacitors are effectively put in parallel is a maximum of 0.6A but most of the time it will be in with COUT, causing a rapid drop in VOUT. No regulator can standby mode, requiring only 2mA. Efficiency at both low deliver enough current to prevent this problem if the load and high load currents is important. With this informa- switch resistance is low and it is driven quickly. The only tion we can calculate L using equation (1), solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • C 1 ⎛ 1. V 2 ⎞ LOAD). L = 1. V 2 ⎜1− ⎟ (3) Thus, a 10µF capacitor charging to 3.3V would require a f I ⎝ V ( )(∆ L) IN ⎠ 250µs rise time, limiting the charging current to about 130mA. Substituting VIN = 4.2V, ∆IL = 240mA and f = 1.5MHz in equation (3) gives:
PC Board Layout Checklist
1. V 2 ⎛ 1. V 2 ⎞ When laying out the printed circuit board, the following L = ⎜1− 2.38 H ⎟ = µ 1. MHz 5 ( mA 240 )⎝ 4. V 2 ⎠ checklist should be used to ensure proper operation of the LTC3406B-1.2. These items are also illustrated graphi- A 2.2µH inductor works well for this application. For best cally in Figures 3 and 4. Check the following in your layout: efficiency choose a 720mA or greater inductor with less 1. The power traces, consisting of the GND trace, the SW than 0.2Ω series resistance. trace and the VIN trace should be kept short, direct and CIN will require an RMS current rating of at least 0.3A ≅ wide. ILOAD(MAX)/2 at temperature and COUT will require an ESR 2. Does the (+) plate of C of less than 0.25Ω. In most cases, a ceramic capacitor will IN connect to VIN as closely as possible? This capacitor provides the AC current to the satisfy this requirement. internal power MOSFETs. VIA TO VOUT VIN 1 VIA TO VIN RUN LTC3406B-1.2 2 5 PIN 1 GND – VOUT VOUT COUT V LTC3406B-1.2 3 4 OUT + SW VIN L1 SW CIN L1 VIN C 3406B12 F03 OUT CIN BOLD LINES INDICATE HIGH CURRENT PATHS GND 3406B12 F04
Figure 3. LTC3406B-1.2 Layout Diagram Figure 4. LTC3406B-1.2 Suggested Layout
sn3406b12 3406b12fs 10
U U W U APPLICATIO S I FOR ATIO
The regulator loop then acts to return VOUT to its steady- 3. Keep the (–) plates of CIN and COUT as close as possible. state value. During this recovery time VOUT can be moni- tored for overshoot or ringing that would indicate a stability
Design Example
problem. For a detailed explanation of switching control As a design example, assume the LTC3406B-1.2 is used loop theory, see Application Note 76. in a single lithium-ion battery-powered cellular phone A second, more severe transient is caused by switching in application. The VIN will be operating from a maximum of loads with large (>1µF) supply bypass capacitors. The 4.2V down to about 2.7V. The load current requirement discharged bypass capacitors are effectively put in parallel is a maximum of 0.6A but most of the time it will be in with COUT, causing a rapid drop in VOUT. No regulator can standby mode, requiring only 2mA. Efficiency at both low deliver enough current to prevent this problem if the load and high load currents is important. With this informa- switch resistance is low and it is driven quickly. The only tion we can calculate L using equation (1), solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • C 1 ⎛ 1. V 2 ⎞ LOAD). L = 1. V 2 ⎜1− ⎟ (3) Thus, a 10µF capacitor charging to 3.3V would require a f I ⎝ V ( )(∆ L) IN ⎠ 250µs rise time, limiting the charging current to about 130mA. Substituting VIN = 4.2V, ∆IL = 240mA and f = 1.5MHz in equation (3) gives:
PC Board Layout Checklist
1. V 2 ⎛ 1. V 2 ⎞ When laying out the printed circuit board, the following L = ⎜1− 2.38 H ⎟ = µ 1. MHz 5 ( mA 240 )⎝ 4. V 2 ⎠ checklist should be used to ensure proper operation of the LTC3406B-1.2. These items are also illustrated graphi- A 2.2µH inductor works well for this application. For best cally in Figures 3 and 4. Check the following in your layout: efficiency choose a 720mA or greater inductor with less 1. The power traces, consisting of the GND trace, the SW than 0.2Ω series resistance. trace and the VIN trace should be kept short, direct and CIN will require an RMS current rating of at least 0.3A ≅ wide. ILOAD(MAX)/2 at temperature and COUT will require an ESR 2. Does the (+) plate of C of less than 0.25Ω. In most cases, a ceramic capacitor will IN connect to VIN as closely as possible? This capacitor provides the AC current to the satisfy this requirement. internal power MOSFETs. VIA TO VOUT VIN 1 VIA TO VIN RUN LTC3406B-1.2 2 5 PIN 1 GND – VOUT VOUT COUT V LTC3406B-1.2 3 4 OUT + SW VIN L1 SW CIN L1 VIN C 3406B12 F03 OUT CIN BOLD LINES INDICATE HIGH CURRENT PATHS GND 3406B12 F04
Figure 3. LTC3406B-1.2 Layout Diagram Figure 4. LTC3406B-1.2 Suggested Layout
sn3406b12 3406b12fs 10
