Datasheet LT1941 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Triple Monolithic Switching Regulator |
| Pages / Page | 24 / 7 — PIN FUNCTIONS. VIN (Pins 1, 2, 22, 25):. BIAS1 (Pin 15):. SW1, SW2, SW3 … |
| File Format / Size | PDF / 237 Kb |
| Document Language | English |
PIN FUNCTIONS. VIN (Pins 1, 2, 22, 25):. BIAS1 (Pin 15):. SW1, SW2, SW3 (Pins 3, 4, 23, 27):. 12GOOD (Pin 16):
Model Line for this Datasheet
Text Version of Document
LT1941
PIN FUNCTIONS VIN (Pins 1, 2, 22, 25):
The VIN pins supply current to
BIAS1 (Pin 15):
The BIAS1 pin supplies the current to the LT1941’s internal circuitry and to the internal power the LT1941’s internal regulator. Tie this pin to the lowest switches. These pins must be tied to the same source and available voltage source above 2.35V (Either VIN, VOUT or locally bypassed. any other available supply).
SW1, SW2, SW3 (Pins 3, 4, 23, 27):
The SW pins are
12GOOD (Pin 16):
The 12GOOD pin is the open-collector the outputs of the internal power switches. Connect these output of an internal comparator. 12GOOD remains low until pins to the inductors and switching diodes. VIN is within 10% of 12V. The pin pulls low when the part is in shutdown. Leave this pin unconnected if unused.
BOOST1, BOOST2 (Pins 5, 24):
The BOOST pins are used to provide drive voltages, higher than the input voltage,
5GOOD (Pin 17):
The 5GOOD pin is the open-collector to the internal bipolar NPN power switches. Tie through output of an internal comparator. 5GOOD remains low until a diode from VOUT or from VIN. VIN is within 10% of 5V. The pin pulls low when the part is in shutdown. Leave this pin unconnected if unused.
PGOOD1, PGOOD2, PGOOD3 (Pins 6, 9, 21):
The PGOOD pins are the open-collector outputs of an internal compara-
NFB (Pin 19):
The LT1941 contains an op amp confi gured tor. PGOOD remains low until the FB pin is within 10% of with an output at FB3, noninverting terminal at GND and the fi nal regulation voltage. As well as indicating output an inverting terminal at NFB. Connect the feedback resistor regulation, the PGOOD pins can sequence the switching network virtual ground at this node if regulating negative regulators. Leave these pins unconnected if unused. The voltages. Otherwise, tie this node to FB3. PGOOD outputs are valid when VIN is greater than 3.5V
PGND (Pin 26):
Tie directly to local ground plane. and any of the RUN/SS pins are high. They are
not
valid when all RUN/SS pins are low.
BIAS2 (Pin 28):
The BIAS2 pin supplies the current to the driver of SW3. Tie this pin to the lowest available
VC1, VC2, VC3 (Pins 7, 10, 18):
The VC pins are the outputs voltage source above 2.5V (Either V of the internal error amps. The voltages on these pins IN, VOUT or any other available supply). control the peak switch currents. These pins are normally used to compensate the control loops. Each switching
Exposed Pad (Pin 29):
Ground. The underside Exposed regulator can be shut down by pulling its respective V Pad metal of the package provides both electrical contact C pin to ground with an NMOS or NPN transistor. to ground and good thermal contact to the printed circuit board. The Exposed Pad must be soldered to the circuit
FB1, FB2, FB3 (Pins 8, 11, 20):
The LT1941 regulates each board ground for proper operation. feedback pin to either 0.628V (FB1, FB2) or 1.25V (FB3). Connect the feedback resistor divider taps to these pins.
RUN/SS1, RUN/SS2, RUN/SS3 (Pins 12, 13, 14):
The RUN/SS pins are used to shut down the individual switching regulators and the internal bias circuits. They also provide a soft-start function. To shut down either regulator, pull the RUN/SS pin to ground with an open drain or collec- tor. Tie a capacitor from this pin to ground to limit switch current during start-up. If neither feature is used, leave these pins unconnected. 1941fb 7
PIN FUNCTIONS VIN (Pins 1, 2, 22, 25):
The VIN pins supply current to
BIAS1 (Pin 15):
The BIAS1 pin supplies the current to the LT1941’s internal circuitry and to the internal power the LT1941’s internal regulator. Tie this pin to the lowest switches. These pins must be tied to the same source and available voltage source above 2.35V (Either VIN, VOUT or locally bypassed. any other available supply).
SW1, SW2, SW3 (Pins 3, 4, 23, 27):
The SW pins are
12GOOD (Pin 16):
The 12GOOD pin is the open-collector the outputs of the internal power switches. Connect these output of an internal comparator. 12GOOD remains low until pins to the inductors and switching diodes. VIN is within 10% of 12V. The pin pulls low when the part is in shutdown. Leave this pin unconnected if unused.
BOOST1, BOOST2 (Pins 5, 24):
The BOOST pins are used to provide drive voltages, higher than the input voltage,
5GOOD (Pin 17):
The 5GOOD pin is the open-collector to the internal bipolar NPN power switches. Tie through output of an internal comparator. 5GOOD remains low until a diode from VOUT or from VIN. VIN is within 10% of 5V. The pin pulls low when the part is in shutdown. Leave this pin unconnected if unused.
PGOOD1, PGOOD2, PGOOD3 (Pins 6, 9, 21):
The PGOOD pins are the open-collector outputs of an internal compara-
NFB (Pin 19):
The LT1941 contains an op amp confi gured tor. PGOOD remains low until the FB pin is within 10% of with an output at FB3, noninverting terminal at GND and the fi nal regulation voltage. As well as indicating output an inverting terminal at NFB. Connect the feedback resistor regulation, the PGOOD pins can sequence the switching network virtual ground at this node if regulating negative regulators. Leave these pins unconnected if unused. The voltages. Otherwise, tie this node to FB3. PGOOD outputs are valid when VIN is greater than 3.5V
PGND (Pin 26):
Tie directly to local ground plane. and any of the RUN/SS pins are high. They are
not
valid when all RUN/SS pins are low.
BIAS2 (Pin 28):
The BIAS2 pin supplies the current to the driver of SW3. Tie this pin to the lowest available
VC1, VC2, VC3 (Pins 7, 10, 18):
The VC pins are the outputs voltage source above 2.5V (Either V of the internal error amps. The voltages on these pins IN, VOUT or any other available supply). control the peak switch currents. These pins are normally used to compensate the control loops. Each switching
Exposed Pad (Pin 29):
Ground. The underside Exposed regulator can be shut down by pulling its respective V Pad metal of the package provides both electrical contact C pin to ground with an NMOS or NPN transistor. to ground and good thermal contact to the printed circuit board. The Exposed Pad must be soldered to the circuit
FB1, FB2, FB3 (Pins 8, 11, 20):
The LT1941 regulates each board ground for proper operation. feedback pin to either 0.628V (FB1, FB2) or 1.25V (FB3). Connect the feedback resistor divider taps to these pins.
RUN/SS1, RUN/SS2, RUN/SS3 (Pins 12, 13, 14):
The RUN/SS pins are used to shut down the individual switching regulators and the internal bias circuits. They also provide a soft-start function. To shut down either regulator, pull the RUN/SS pin to ground with an open drain or collec- tor. Tie a capacitor from this pin to ground to limit switch current during start-up. If neither feature is used, leave these pins unconnected. 1941fb 7
