Datasheet LTC3418 (Analog Devices) - 8

LTC3418
operaTion Main Control Loop Burst Mode Operation
The LTC3418 is a monolithic, constant frequency, current Connecting the SYNC/MODE pin to a voltage in the range mode step-down DC/DC converter. During normal opera- of 0V to 1V enables Burst Mode operation. In Burst Mode tion, the internal top power switch (P-channel MOSFET) is operation, the internal power MOSFETs operate intermit- turned on at the beginning of each clock cycle. Current in tently at light loads. This increases efficiency by minimiz- the inductor increases until the current comparator trips ing switching losses. During Burst Mode operation, the and turns off the top power MOSFET. The peak inductor minimum peak inductor current is externally set by the current at which the current comparator shuts off the top voltage on the SYNC/MODE pin and the voltage on the ITH power switch is controlled by the voltage on the ITH pin. pin is monitored by the burst comparator to determine The error amplifier adjusts the voltage on the ITH pin by when sleep mode is enabled and disabled. When the comparing the feedback signal from a resistor divider on average inductor current is greater than the load current, the VFB pin with an internal 0.8V reference. When the load the voltage on the ITH pin drops. As the ITH voltage falls current increases, it causes a reduction in the feedback below 350mV, the burst comparator trips and enables voltage relative to the reference. The error amplifier raises sleep mode. During sleep mode, the top power MOSFET the ITH voltage until the average inductor current matches is held off while the load current is solely supplied by the the new load current. When the top power MOSFET shuts output capacitor. When the output voltage drops, the top off, the synchronous power switch (N-channel MOSFET) and bottom power MOSFETs begin switching to bring the turns on until either the bottom current limit is reached or output back into regulation. This process repeats at a rate the beginning of the next clock cycle. The bottom current that is dependent on the load demand. limit is set at –8A for force continuous mode and 0A for Pulse skipping operation can be implemented by connect- Burst Mode operation. ing the SYNC/MODE pin to ground. This forces the burst The operating frequency is externally set by an external clamp level to be at 0V. As the load current decreases, the resistor connected between the RT pin and ground. The peak inductor current will be determined by the voltage practical switching frequency can range from 300kHz to on the ITH pin until the ITH voltage drops below 400mV. At 4MHz. this point, the peak inductor current is determined by the Overvoltage and undervoltage comparators will pull the minimum on-time of the current comparator. If the load PGOOD output low if the output voltage comes out of demand is less than the average of the minimum on-time regulation by ±7.5%. In an overvoltage condition, the top inductor current, switching cycles will be skipped to keep power MOSFET is turned off and the bottom power MOSFET the output voltage in regulation. is switched on until either the overvoltage condition clears
Frequency Synchronization
or the bottom MOSFET’s current limit is reached. The internal oscillator of the LTC3418 can by synchronized
Forced Continuous
to an external clock connected to the SYNC/MODE pin. Connecting the SYNC/MODE pin to SV The frequency of the external clock can be in the range IN will disable Burst Mode operation and force continuous current operation. of 300kHz to 4MHz. At light loads, forced continuous mode operation is less For this application, the oscillator timing resistor should efficient than Burst Mode operation, but may be desirable in be chosen to correspond to a frequency that is 25% lower some applications where it is necessary to keep switching than the synchronization frequency. During synchroniza- harmonics out of a signal band. The output voltage ripple tion, the burst clamp is set to 0V, and each switching cycle is minimized in this mode. begins at the falling edge of the clock signal. 3418fc 8 For more information www.linear.com/LTC3418 Document Outline Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts