Datasheet LTC1627 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Monolithic Synchronous Step-Down Switching Regulator |
| Pages / Page | 16 / 7 — OPERATIO. Dropout Operation. Figure 2. Using a Charge Pump to Bias VDR. … |
| File Format / Size | PDF / 240 Kb |
| Document Language | English |
OPERATIO. Dropout Operation. Figure 2. Using a Charge Pump to Bias VDR. Undervoltage Lockout
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LTC1627
U OPERATIO
load slightly allows constant frequency PWM operation VDR to resume. C1 0.1µF LTC1627 V V IN IN < 4.5V Frequency synchronization is inhibited when the feedback D1 L1 voltage V SW V FB is below 0.6V. This prevents the external clock OUT C2 + from interfering with the frequency foldback for short- COUT 0.1µF 100µF circuit protection. D2 1627 F02
Dropout Operation Figure 2. Using a Charge Pump to Bias VDR
When the input supply voltage decreases toward the out- put voltage, the duty cycle increases toward the maximum the charge pump at VIN ≥ 4.5V is not recommended to on-time. Further reduction of the supply voltage forces the ensure that (VIN – VDR) does not exceed its absolute main switch to remain on for more than one cycle until it maximum voltage. reaches 100% duty cycle. The output voltage will then be When V determined by the input voltage minus the voltage drop IN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the P-channel across the P-channel MOSFET and the inductor. MOSFET continuously. When the VDR charge pump is In Burst Mode operation or pulse skipping mode operation enabled, a dropout detector counts the number of oscilla- (externally synchronized) with the output lightly loaded, tor cycles that the P-channel MOSFET remains on, and the LTC1627 transitions through continuous mode as it periodically forces a brief off period to allow C1 to enters dropout. recharge. 100% duty cycle is allowed when VDR is grounded.
Undervoltage Lockout Slope Compensation and Inductor Peak Current
A precision undervoltage lockout shuts down the LTC1627 Slope compensation provides stability by preventing when V subharmonic oscillations. It works by internally adding a IN drops below 2.5V, making it ideal for single lithium-ion battery applications. In lockout, the LTC1627 ramp to the inductor current signal at duty cycles in excess draws only several microamperes, which is low enough to of 40%. As a result, the maximum inductor peak current prevent deep discharge and possible damage to the lithium- is lower for VOUT/VIN > 0.4 than when VOUT/VIN < 0.4. See ion battery nearing its end of charge. A 150mV hysteresis the inductor peak current as a function of duty cycle graph ensures reliable operation with noisy supplies. in Figure 3. The worst-case peak current reduction occurs with the oscillator synchronized at its minimum frequency,
Low Supply Operation
i.e., to a clock just above the oscillator free-running The LTC1627 is designed to operate down to 2.65V supply 950 voltage. At this voltage the converter is most likely to be 900 WITHOUT running at high duty cycles or in dropout where the main EXTERNAL 850 CLOCK SYNC switch is on continuously. Hence, the I2R loss is due 800 mainly to the RDS(ON) of the P-channel MOSFET. See WORST CASE 750 Efficiency Considerations in the Applications Information EXTERNAL 700 CLOCK SYNC section. 650 When VIN is low (< 4.5V) the RDS(ON) of the P-channel 600 MOSFET can be lowered by driving its gate below ground. 550 The top P-channel MOSFET driver makes use of a floating MAXIMUM INDUCTOR PEAK CURRENT (mA) VIN = 5V 500 return pin, V 0 10 20 30 40 50 60 70 80 90 100 DR, to allow biasing below GND. A simple DUTY CYCLE (%) charge pump bootstrapped to the SW pin realizes a 1627 F03 negative voltage at the VDR pin as shown in Figure 2. Using
Figure 3. Maximum Inductor Peak Current vs Duty Cycle
7
U OPERATIO
load slightly allows constant frequency PWM operation VDR to resume. C1 0.1µF LTC1627 V V IN IN < 4.5V Frequency synchronization is inhibited when the feedback D1 L1 voltage V SW V FB is below 0.6V. This prevents the external clock OUT C2 + from interfering with the frequency foldback for short- COUT 0.1µF 100µF circuit protection. D2 1627 F02
Dropout Operation Figure 2. Using a Charge Pump to Bias VDR
When the input supply voltage decreases toward the out- put voltage, the duty cycle increases toward the maximum the charge pump at VIN ≥ 4.5V is not recommended to on-time. Further reduction of the supply voltage forces the ensure that (VIN – VDR) does not exceed its absolute main switch to remain on for more than one cycle until it maximum voltage. reaches 100% duty cycle. The output voltage will then be When V determined by the input voltage minus the voltage drop IN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the P-channel across the P-channel MOSFET and the inductor. MOSFET continuously. When the VDR charge pump is In Burst Mode operation or pulse skipping mode operation enabled, a dropout detector counts the number of oscilla- (externally synchronized) with the output lightly loaded, tor cycles that the P-channel MOSFET remains on, and the LTC1627 transitions through continuous mode as it periodically forces a brief off period to allow C1 to enters dropout. recharge. 100% duty cycle is allowed when VDR is grounded.
Undervoltage Lockout Slope Compensation and Inductor Peak Current
A precision undervoltage lockout shuts down the LTC1627 Slope compensation provides stability by preventing when V subharmonic oscillations. It works by internally adding a IN drops below 2.5V, making it ideal for single lithium-ion battery applications. In lockout, the LTC1627 ramp to the inductor current signal at duty cycles in excess draws only several microamperes, which is low enough to of 40%. As a result, the maximum inductor peak current prevent deep discharge and possible damage to the lithium- is lower for VOUT/VIN > 0.4 than when VOUT/VIN < 0.4. See ion battery nearing its end of charge. A 150mV hysteresis the inductor peak current as a function of duty cycle graph ensures reliable operation with noisy supplies. in Figure 3. The worst-case peak current reduction occurs with the oscillator synchronized at its minimum frequency,
Low Supply Operation
i.e., to a clock just above the oscillator free-running The LTC1627 is designed to operate down to 2.65V supply 950 voltage. At this voltage the converter is most likely to be 900 WITHOUT running at high duty cycles or in dropout where the main EXTERNAL 850 CLOCK SYNC switch is on continuously. Hence, the I2R loss is due 800 mainly to the RDS(ON) of the P-channel MOSFET. See WORST CASE 750 Efficiency Considerations in the Applications Information EXTERNAL 700 CLOCK SYNC section. 650 When VIN is low (< 4.5V) the RDS(ON) of the P-channel 600 MOSFET can be lowered by driving its gate below ground. 550 The top P-channel MOSFET driver makes use of a floating MAXIMUM INDUCTOR PEAK CURRENT (mA) VIN = 5V 500 return pin, V 0 10 20 30 40 50 60 70 80 90 100 DR, to allow biasing below GND. A simple DUTY CYCLE (%) charge pump bootstrapped to the SW pin realizes a 1627 F03 negative voltage at the VDR pin as shown in Figure 2. Using
Figure 3. Maximum Inductor Peak Current vs Duty Cycle
7
