Datasheet LTC3838-2 (Analog Devices) - 10

LTC3838-2
pin FuncTions V + DFB2 (Pin 1):
Differential Feedback Amplifier Positive frequency will be set by the RT pin. To synchronize other (+) Input of Channel 2. As shown in the Functional Dia- controllers, it can be connected to their MODE/PLLIN pins. gram, connect this pin to a 3-resistor feedback divider
SGND (Pin 7):
Signal Ground. All small-signal analog and network, which is composed of RDFB1 and RDFB2 from compensation components should be connected to this this pin to the negative and positive terminals of VOUT2 ground. Connect SGND to the exposed pad and PGND pin respectively, and a third resistor from this pin to the re- using a single PCB trace. mote ground of external reference voltage (V – REF2 ). The third resistor must have a value equal to RDFB1//RDFB2
RT (Pin 8):
Clock Generator Frequency Programming Pin. for accurate differential regulation. With the 3-resistor Connect an external resistor from RT to SGND to program feedback divider network, the LTC3838-2 will regulate the the switching frequency between 200kHz and 2MHz. An differential output (V + – + – OUT2 – VOUT2 ) to (VREF2 – VREF2 ) external clock applied to MODE/PLLIN should be within • (RDFB1 + RDFB2)/RDFB1. ±30% of this programmed frequency to ensure frequency lock. When the RT pin is floating, the frequency is internally
EXTVREF2 (Pin 2):
External Reference Voltage for Channel 2. set to be slightly under 200kHz. Connect this pin to the positive (+) terminal of external reference voltage (V + REF2 ). The internal feedback voltage
PHASMD (Pin 9):
Phase Selector Input. This pin V + – FB2 (i.e., 2 • VDFB2 – VDFB2 ) will be regulated to the determines the relative phases of channels and the voltage on this pin, so that the differential VOUT2 equals CLKOUT signal. With zero phase being defined as the (V + – REF2 – VREF2 ) • (RDFB1 + RDFB2)/RDFB1. When this pin rising edge of TG1: Pulling this pin to SGND locks TG2 to is less than around 100mV, the TRACK/SS2 pin will be 180°, and CLKOUT to 60°. Connecting this pin to INTVCC pulled to ground to keep channel 2 from switching. Channel locks TG2 to 240° and CLKOUT to 120°. Floating this pin 2’s overvoltage and undervoltage thresholds are ±7.5% of locks TG2 to 180° and CLKOUT to 90°. this EXTVREF2 pin voltage. For valid PGOOD2 signal upon
ITH1, ITH2 (Pin 10, Pin 3):
Current Control Threshold. This startup and to avoid prebiased VOUT2 (if any) being pulled pin is the output of the error amplifier and the switching down, apply EXTVREF2 before RUN2 is enabled. Normal regulator’s compensation point. The current comparator operations are only guaranteed with an EXTVREF2 of 0.4V threshold increases with this control voltage. The voltage minimum and 1.5V maximum at INTVCC ≥ 4V, or 2.5V ranges from 0V to 2.4V, with 0.8V corresponding to zero maximum at INTVCC ≥ 5V. Note its small bias current (see sense voltage (zero inductor valley current). the Electrical Characteristics section) may cause offset if external R-C filter is connected to this pin for either limit-
TRACK/SS1, TRACK/SS2 (Pin 11, Pin 4):
External Track- ing voltage slew rate or filtering noise. ing and Soft-Start Input. Channel 1 regulates the feedback voltage V + – V – to the smaller
MODE/PLLIN (Pin 5):
Operation Mode Selection or Exter- FB1 = VOUTSENSE1 OUTSENSE1 of 0.6V or the voltage on the TRACK/SS1 pin. Channel 2 nal Clock Synchronization Input. When this pin is tied to regulates the V + – V – to the smaller INTV FB2 = 2 • VDFB2 DFB2 CC, forced continuous mode operation is selected. Ty- of the voltage on the EXTV ing this pin to SGND al ows discontinuous mode operation. REF2 pin or the voltage on the TRACK/SS2 pin. An internal 1µA temperature-independent When an external clock is applied at this pin, both channels pull-up current source is connected to each TRACK/SS operate in forced continuous mode and synchronize to the pin. A capacitor to ground at this pin sets the ramp time external clock. This pin has an internal 600k pull-down to the final regulated output voltage. Alternatively, another resistor to SGND. voltage supply connected to this pin allows the output to
CLKOUT (Pin 6):
Clock Output of Internal Clock Genera- track the other supply during start-up. In applications that tor. Its output level swings between INTVCC and SGND. operate simultaneously at both high EXTVREF2 (>1.5V) If clock input is present at the MODE/PLLIN pin, it will and low VIN (<6V) pin voltages, external pull-up (resistor be synchronized to the input clock, with phase set by the or fixed current from INTVCC) may be required so that PHASMD pin. If no clock is present at MODE/PLLIN, its TRACK/SS2 rises well above EXTVREF2. 38382fa 10 For more information www.linear.com/3838-2 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts