Datasheet LTC3861 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing |
| Pages / Page | 38 / 9 — pin FuncTions. VSNSOUT1 (Pin 5), VSNSOUT2 (Pin 6):. ISNS1P (Pin 25), … |
| File Format / Size | PDF / 996 Kb |
| Document Language | English |
pin FuncTions. VSNSOUT1 (Pin 5), VSNSOUT2 (Pin 6):. ISNS1P (Pin 25), ISNS2P (Pin 22):. FREQ (Pin 12):
Model Line for this Datasheet
Text Version of Document
LTC3861
pin FuncTions VSNSOUT1 (Pin 5), VSNSOUT2 (Pin 6):
Differential Am-
ISNS1P (Pin 25), ISNS2P (Pin 22):
Current Sense Ampli- plifier Output. Connect to FB1, FB2 with a compensation fier (+) Input. The (+) input to the current sense amplifier network for remote VOUT sensing. is normally connected to the midpoint of the inductor’s
FREQ (Pin 12):
Frequency Set/Select Pin. This pin sources parallel RC sense circuit or to the node between the induc- 20µA current. If CLKIN is high or floating, then a resistor tor and sense resistor if using a discrete sense resistor. between this pin and SGND sets the switching frequency. If
ILIM1 (Pin 27), ILIM2 (Pin 20):
Current Comparator Sense CLKIN is low, the logic state of this pin selects an internal Voltage Limit Selection Pin. Connect a resistor from this 600kHz or 1MHz preset frequency. pin to SGND. This pin sources 20µA. The resultant voltage
CLKIN (Pin 13):
External Clock Synchronization Input. sets the threshold for overcurrent protection. Applying an external clock between 250kHz to 2.25MHz
RUN1 (Pin 28), RUN2 (Pin 19):
Run Control Inputs. A will cause the switching frequency to synchronize to the voltage above 2.25V on either pin turns on the IC. How- clock. CLKIN is pulled high to VCC by a 50k internal resis- ever, forcing either of these pins below 2V causes the tor. The rising edge of the CLKIN input waveform will align IC to shut down that particular channel. There are 1.5µA with the rising edge of PWM1 in closed-loop operation. If pull-up currents for these pins. CLKIN is high or floating, a resistor from the FREQ pin to
PWM1 (Pin 29), PWM2 (Pin 18):
(Top) Gate Signal Out- SGND sets the switching frequency. If CLKIN is low, the put. This signal goes to the PWM or top gate input of the FREQ pin logic state selects an internal 600kHz or 1MHz external gate driver or integrated driver MOSFET. This is preset frequency. a three-state compatible output.
CLKOUT (Pin 14):
Digital Output Used for Daisychaining
PWMEN1 (Pin 30), PWMEN2 (Pin 17):
Enable Pin for Multiple LTC3861 ICs in Multiphase Systems. The PHSMD Non-Three-State compatible drivers. This pin has an in- pin voltage controls the relationship between CH1 and CH2 ternal open-drain pull-up to V as well as between CH1 and CLKOUT. When both RUN pins CC. An external resistor to SGND is required. This pin is low when the corresponding are driven low, the CLKOUT pin is actively pulled up to VCC. PWM pin is high impedance.
PHSMD (Pin 15):
Phase Mode Pin. The PHSMD pin volt-
PGOOD1 (Pin 31), PGOOD2 (Pin 16):
Power Good Indi- age programs the phase relationship between CH1 and cator Output for Each Channel. Open-drain logic out that CH2 rising PWM signals, as well as the phase relationship is pulled to SGND when either channel output exceeds a between CH1 PWM signal and CLKOUT. Floating this pin ±10% regulation window, after the internal 30µs power or connecting it to either VCC or SGND changes the phase bad mask timer expires. relationship between CH1, CH2 and CLKOUT.
I SGND (Pins 21, 26, Exposed Pad Pin 37):
Signal Ground.
AVG (Pin 32):
Average Current Output Pin. A capacitor tied to ground from this pin stores a voltage proportional Pins 21, 26, and 37 are electrically connected internally. to the instantaneous average current of the master when The exposed pad must be soldered to the PCB ground multiple outputs are paralleled together in a master-slave for rated thermal performance. All soft-start, small-signal configuration. Only the master phase contributes infor- and compensation components should return to SGND. mation to this average through an internal resistor when
ISNS1N (Pin 24), ISNS2N (Pin 23):
Current Sense Am- in current sharing mode. The IAVG pin ignores channels plifier (–) Input. The (–) input to the current amplifier is configured for independent operation, hence the pin normally connected to the respective VOUT at the inductor. should be connected to SGND when the controller drives independent outputs. For single output converters using two or more ICs, tie all of the IAVG pins together. The total capacitance on the IAVG bus should range from 47pF to 220pF, inclusive, with the typical value being 100pF. 3861fb For more information www.linear.com/LTC3861 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Related Parts
pin FuncTions VSNSOUT1 (Pin 5), VSNSOUT2 (Pin 6):
Differential Am-
ISNS1P (Pin 25), ISNS2P (Pin 22):
Current Sense Ampli- plifier Output. Connect to FB1, FB2 with a compensation fier (+) Input. The (+) input to the current sense amplifier network for remote VOUT sensing. is normally connected to the midpoint of the inductor’s
FREQ (Pin 12):
Frequency Set/Select Pin. This pin sources parallel RC sense circuit or to the node between the induc- 20µA current. If CLKIN is high or floating, then a resistor tor and sense resistor if using a discrete sense resistor. between this pin and SGND sets the switching frequency. If
ILIM1 (Pin 27), ILIM2 (Pin 20):
Current Comparator Sense CLKIN is low, the logic state of this pin selects an internal Voltage Limit Selection Pin. Connect a resistor from this 600kHz or 1MHz preset frequency. pin to SGND. This pin sources 20µA. The resultant voltage
CLKIN (Pin 13):
External Clock Synchronization Input. sets the threshold for overcurrent protection. Applying an external clock between 250kHz to 2.25MHz
RUN1 (Pin 28), RUN2 (Pin 19):
Run Control Inputs. A will cause the switching frequency to synchronize to the voltage above 2.25V on either pin turns on the IC. How- clock. CLKIN is pulled high to VCC by a 50k internal resis- ever, forcing either of these pins below 2V causes the tor. The rising edge of the CLKIN input waveform will align IC to shut down that particular channel. There are 1.5µA with the rising edge of PWM1 in closed-loop operation. If pull-up currents for these pins. CLKIN is high or floating, a resistor from the FREQ pin to
PWM1 (Pin 29), PWM2 (Pin 18):
(Top) Gate Signal Out- SGND sets the switching frequency. If CLKIN is low, the put. This signal goes to the PWM or top gate input of the FREQ pin logic state selects an internal 600kHz or 1MHz external gate driver or integrated driver MOSFET. This is preset frequency. a three-state compatible output.
CLKOUT (Pin 14):
Digital Output Used for Daisychaining
PWMEN1 (Pin 30), PWMEN2 (Pin 17):
Enable Pin for Multiple LTC3861 ICs in Multiphase Systems. The PHSMD Non-Three-State compatible drivers. This pin has an in- pin voltage controls the relationship between CH1 and CH2 ternal open-drain pull-up to V as well as between CH1 and CLKOUT. When both RUN pins CC. An external resistor to SGND is required. This pin is low when the corresponding are driven low, the CLKOUT pin is actively pulled up to VCC. PWM pin is high impedance.
PHSMD (Pin 15):
Phase Mode Pin. The PHSMD pin volt-
PGOOD1 (Pin 31), PGOOD2 (Pin 16):
Power Good Indi- age programs the phase relationship between CH1 and cator Output for Each Channel. Open-drain logic out that CH2 rising PWM signals, as well as the phase relationship is pulled to SGND when either channel output exceeds a between CH1 PWM signal and CLKOUT. Floating this pin ±10% regulation window, after the internal 30µs power or connecting it to either VCC or SGND changes the phase bad mask timer expires. relationship between CH1, CH2 and CLKOUT.
I SGND (Pins 21, 26, Exposed Pad Pin 37):
Signal Ground.
AVG (Pin 32):
Average Current Output Pin. A capacitor tied to ground from this pin stores a voltage proportional Pins 21, 26, and 37 are electrically connected internally. to the instantaneous average current of the master when The exposed pad must be soldered to the PCB ground multiple outputs are paralleled together in a master-slave for rated thermal performance. All soft-start, small-signal configuration. Only the master phase contributes infor- and compensation components should return to SGND. mation to this average through an internal resistor when
ISNS1N (Pin 24), ISNS2N (Pin 23):
Current Sense Am- in current sharing mode. The IAVG pin ignores channels plifier (–) Input. The (–) input to the current amplifier is configured for independent operation, hence the pin normally connected to the respective VOUT at the inductor. should be connected to SGND when the controller drives independent outputs. For single output converters using two or more ICs, tie all of the IAVG pins together. The total capacitance on the IAVG bus should range from 47pF to 220pF, inclusive, with the typical value being 100pF. 3861fb For more information www.linear.com/LTC3861 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Related Parts
