Datasheet LTC3858-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low IQ, Dual 2-Phase Synchronous Step-Down Controller |
| Pages / Page | 38 / 10 — FUNCTIONAL DIAGRAM. OPERATION. Main Control Loop |
| File Format / Size | PDF / 439 Kb |
| Document Language | English |
FUNCTIONAL DIAGRAM. OPERATION. Main Control Loop
Model Line for this Datasheet
Text Version of Document
LTC3858-1
FUNCTIONAL DIAGRAM
INTVCC VIN DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB CB TG DROP TOP PGOOD1 + OUT C 0.88V IN D DET BOT – SW TOP ON VFB1 S Q + INTVCC R – Q 0.72V SWITCH BG SHDN LOGIC BOT C PGND OUT FREQ 20μA VOUT VCO CLK2 + R 0.425V SENSE CLK1 SLEEP L – ICMP IR + + PFD – – – + + – 3mV SENSE+ SYNC 2(VFB) PLLIN/MODE DET 0.45V SENSE– 100k SLOPE COMP VFB R + B VIN EA – 0.80V R TRACK/SS A EXTVCC + OV – C 0.88V C ITH 5.1V 5.1V LDO LDO 0.5μA SHDN C R EN EN C2 C RST FOLDBACK + 11V 2(VFB) – 4.7V 1μA SS SGND INTVCC RUN SHORT CKT SHDN CSS LATCHOFF 10μA 38581 FD
OPERATION Main Control Loop
the VFB pin (which is generated with an external resistor divider connected across the output voltage, V The LTC3858-1 uses a constant frequency, current mode OUT , to ground) to the internal 0.800V reference voltage. When the step-down architecture with the two controller channels load current increases, it causes a slight decrease in V operating 180 degrees out of phase. During normal op- FB relative to the reference, which causes the EA to increase eration, each external top MOSFET is turned on when the the I clock for that channel sets the RS latch, and is turned off TH voltage until the average inductor current matches the new load current. when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and After the top MOSFET is turned off each cycle, the bottom resets the latch is controlled by the voltage on the ITH pin, MOSFET is turned on until either the inductor current starts which is the output of the error amplifi er, EA. The error to reverse, as indicated by the current comparator IR, or amplifi er compares the output voltage feedback signal at the beginning of the next clock cycle. 38581fd 10
FUNCTIONAL DIAGRAM
INTVCC VIN DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB CB TG DROP TOP PGOOD1 + OUT C 0.88V IN D DET BOT – SW TOP ON VFB1 S Q + INTVCC R – Q 0.72V SWITCH BG SHDN LOGIC BOT C PGND OUT FREQ 20μA VOUT VCO CLK2 + R 0.425V SENSE CLK1 SLEEP L – ICMP IR + + PFD – – – + + – 3mV SENSE+ SYNC 2(VFB) PLLIN/MODE DET 0.45V SENSE– 100k SLOPE COMP VFB R + B VIN EA – 0.80V R TRACK/SS A EXTVCC + OV – C 0.88V C ITH 5.1V 5.1V LDO LDO 0.5μA SHDN C R EN EN C2 C RST FOLDBACK + 11V 2(VFB) – 4.7V 1μA SS SGND INTVCC RUN SHORT CKT SHDN CSS LATCHOFF 10μA 38581 FD
OPERATION Main Control Loop
the VFB pin (which is generated with an external resistor divider connected across the output voltage, V The LTC3858-1 uses a constant frequency, current mode OUT , to ground) to the internal 0.800V reference voltage. When the step-down architecture with the two controller channels load current increases, it causes a slight decrease in V operating 180 degrees out of phase. During normal op- FB relative to the reference, which causes the EA to increase eration, each external top MOSFET is turned on when the the I clock for that channel sets the RS latch, and is turned off TH voltage until the average inductor current matches the new load current. when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and After the top MOSFET is turned off each cycle, the bottom resets the latch is controlled by the voltage on the ITH pin, MOSFET is turned on until either the inductor current starts which is the output of the error amplifi er, EA. The error to reverse, as indicated by the current comparator IR, or amplifi er compares the output voltage feedback signal at the beginning of the next clock cycle. 38581fd 10
