Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 4

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ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549
The ADSP-BF54x Blackfin processors are completely code- and memory spaces, including external DDR (either standard or pin-compatible. They differ only with respect to their perfor- mobile, depending on the device) and asynchronous memory. mance, on-chip memory, and selection of I/O peripherals. Multiple on-chip buses running at up to 133 MHz provide Specific performance, memory, and feature configurations are enough bandwidth to keep the processor core running along shown in Table 1. with activity on all of the on-chip and external peripherals. By integrating a rich set of industry-leading system peripherals The ADSP-BF54x Blackfin processors include an on-chip volt- and memory, Blackfin processors are the platform of choice for age regulator in support of the dynamic power management next-generation applications that require RISC-like program- capability. The voltage regulator provides a range of core volt- mability, multimedia support, and leading-edge signal age levels when supplied from VDDEXT. The voltage regulator can processing in one integrated package. be bypassed at the user’s discretion.
LOW POWER ARCHITECTURE BLACKFIN PROCESSOR CORE
Blackfin processors provide world-class power management As shown in Figure 2 on Page 5, the Blackfin processor core and performance. Blackfin processors are designed in a low contains two 16-bit multipliers, two 40-bit accumulators, two power and low voltage design methodology and feature on-chip 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- dynamic power management, the ability to vary both the voltage tation units process 8-, 16-, or 32-bit data from the register file. and frequency of operation to significantly lower overall power The compute register file contains eight 32-bit registers. When consumption. Reducing both voltage and frequency can result performing compute operations on 16-bit operand data, the in a substantial reduction in power consumption as compared register file operates as 16 independent 16-bit registers. All to reducing only the frequency of operation. This translates into operands for compute operations come from the multiported longer battery life for portable appliances. register file and instruction constant fields.
SYSTEM INTEGRATION
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. The ADSP-BF54x Blackfin processors are highly integrated Signed and unsigned formats, rounding, and saturation are system-on-a-chip solutions for the next generation of embed- supported. ded network connected applications. By combining industry- standard interfaces with a high performance signal processing The ALUs perform a traditional set of arithmetic and logical core, users can develop cost-effective solutions quickly without operations on 16- or 32-bit data. In addition, many special the need for costly external components. The system peripherals instructions are included to accelerate various signal processing include a high speed USB OTG (On-the-Go) controller with tasks. These include bit operations such as field extract and pop- integrated PHY, CAN 2.0B controllers, TWI controllers, UART ulation count, modulo 232 multiply, divide primitives, saturation ports, SPI ports, serial ports (SPORTs), ATAPI controller, and rounding, and sign/exponent detection. The set of video SD/SDIO controller, a real-time clock, a watchdog timer, LCD instructions include byte alignment and packing operations, controller, and multiple enhanced parallel peripheral interfaces. 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations.
BLACKFIN PROCESSOR PERIPHERALS
Also provided are the compare/select and vector search The ADSP-BF54x processors contain a rich set of peripherals instructions. connected to the core via several high bandwidth buses, provid- For certain instructions, two 16-bit ALU operations can be per- ing flexibility in system configuration as well as excellent overall formed simultaneously on register pairs (a 16-bit high half and system performance (see Figure 1 on Page 1). The general- 16-bit low half of a compute register). By also using the second purpose peripherals include functions such as UARTs, SPI, ALU, quad 16-bit operations are possible. TWI, timers with pulse width modulation (PWM) and pulse The 40-bit shifter can perform shifts and rotates and is used to measurement capability, general-purpose I/O pins, a real-time support normalization, field extract, and field deposit clock, and a watchdog timer. This set of functions satisfies a instructions. wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP- The program sequencer controls the flow of instruction execu- BF54x processors contain dedicated network communication tion, including instruction alignment and decoding. For modules and high speed serial and parallel ports, an interrupt program flow control, the sequencer supports PC relative and controller for flexible management of interrupts from the on- indirect conditional jumps (with static branch prediction), and chip peripherals or external sources, and power management subroutine calls. Hardware is provided to support zero-over- control functions to tailor the performance and power charac- head looping. The architecture is fully interlocked, meaning that teristics of the processor and system to many application the programmer need not manage the pipeline when executing scenarios. instructions with data dependencies. All of the peripherals, except for general-purpose I/O, CAN, The address arithmetic unit provides two addresses for simulta- TWI, real-time clock, and timers, are supported by a flexible neous dual fetches from memory. It contains a multiported DMA structure. There are also separate memory DMA channels register file consisting of four sets of 32-bit index, modify, dedicated to data transfers between the processor's various Rev. E | Page 4 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide