Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 7

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ADSP-BF539/ ADSP-BF539F
• Nonmaskable Interrupt (NMI) – The NMI event can be register may be read while in supervisor mode and may generated by the software watchdog timer or by the NMI only be written while in supervisor mode when the corre- input signal to the processor. The NMI event is frequently sponding IMASK bit is cleared. used as a power-down indicator to initiate an orderly shut- • CEC interrupt mask register (IMASK) – The IMASK regis- down of the system. ter controls the masking and unmasking of individual • Exceptions – Events that occur synchronously to program events. When a bit is set in the IMASK register, that event is flow (i.e., the exception will be taken before the instruction unmasked and will be processed by the CEC when asserted. is allowed to complete). Conditions such as data alignment A cleared bit in the IMASK register masks the event, violations and undefined instructions cause exceptions. preventing the processor from servicing the event even • Interrupts – Events that occur asynchronously to program though the event can be latched in the ILAT register. This flow. They are caused by input pins, timers, and other register can be read or written while in supervisor mode. peripherals, as well as by an explicit software instruction. General-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When • CEC interrupt pending register (IPEND) – The IPEND an event is triggered, the state of the processor is saved on the register keeps track of all nested events. A set bit in the supervisor stack. IPEND register indicates whether the event is currently active or nested at some level. This register is updated auto- The ADSP-BF539/ADSP-BF539F processor’s event controller matically by the controller but can be read while in consists of two stages, the core event controller (CEC) and the supervisor mode. system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and con- The SIC allows further control of event processing by providing trol all system events. Conceptually, interrupts from the three 32-bit interrupt control and status registers. Each register peripherals enter into the SIC and are then routed directly into contains a bit corresponding to each of the peripheral interrupt the general-purpose interrupts of the CEC. events shown in Table 3 on Page 8. • SIC interrupt mask registers (SIC_IMASKx) – These regis-
Core Event Controller (CEC)
ters control the masking and unmasking of each peripheral The CEC supports nine general-purpose interrupts (IVG15–7), interrupt event. When a bit is set in these registers, that in addition to the dedicated interrupt and exception events. Of peripheral event is unmasked and will be processed by the these general-purpose interrupts, the two lowest priority inter- system when asserted. A cleared bit in these registers masks rupts (IVG15–14) are recommended to be reserved for software the peripheral event, preventing the processor from servic- interrupt handlers, leaving seven prioritized interrupt inputs to ing the event. support the processor’s peripherals. Table 2 describes the inputs • SIC interrupt status registers (SIC_ISRx) – As multiple to the CEC, identifies their names in the event vector table peripherals can be mapped to a single event, these registers (EVT), and lists their priorities. allow the software to determine which peripheral event
System Interrupt Controller (SIC)
source triggered the interrupt. A set bit indicates that the peripheral is asserting the interrupt, and a cleared bit indi- The system interrupt controller (SIC) provides the mapping and cates that the peripheral is not asserting the event. routing of events from the many peripheral interrupt sources to • SIC interrupt wake-up enable registers (SIC_IWRx) – By the prioritized general-purpose interrupt inputs of the CEC. enabling the corresponding bit in these registers, a periph- Although the ADSP-BF539/ADSP-BF539F processors provide a eral can be configured to wake up the processor, should the default mapping, the user can alter the mappings and priorities core be idled or in sleep mode when the event is generated. of interrupt events by writing the appropriate values into the (For more information, see Dynamic Power Management interrupt assignment registers (SIC_IARx). Table 3 describes on Page 13.) the inputs into the SIC and the default mappings into the CEC. Because multiple interrupt sources can map to a single general-
Event Control
purpose interrupt, multiple pulse assertions can occur simulta- The ADSP-BF539/ADSP-BF539F processors provide the user neously, before or during interrupt processing for an interrupt with a very flexible mechanism to control the processing of event already detected on this interrupt input. The IPEND reg- events. In the CEC, three registers are used to coordinate and ister contents are monitored by the SIC as the interrupt control events. Each register is 32 bits wide: acknowledgement. • CEC interrupt latch register (ILAT) – The ILAT register The appropriate ILAT register bit is set when an interrupt rising indicates when events have been latched. The appropriate edge is detected (detection requires two core clock cycles). The bit is set when the processor has latched the event and is bit is cleared when the respective IPEND register bit is set. The cleared when the event has been accepted into the system. IPEND bit indicates that the event has entered into the proces- This register is updated automatically by the controller, but sor pipeline. At this point the CEC will recognize and queue the it can also be written to clear (cancel) latched events. This next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the Rev. F | Page 7 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide