Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 5

link to page 5
ADSP-BF538/ ADSP-BF538F
The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported
0xFFFF FFFF
register file consisting of four sets of 32-bit index, modify,
CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000
length, and base registers (for circular buffering), and eight
SYSTEM MMR REGISTERS (2M BYTES)
additional 32-bit pointer registers (for C style indexed stack
0xFFC0 0000 RESERVED
manipulation).
0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES)
Blackfin processors support a modified Harvard architecture in
0xFFB0 0000 RESERVED P
combination with a hierarchical memory structure. Level 1 (L1)
A 0xFFA1 4000 M INSTRUCTION SRAM / CACHE (16K BYTES) Y
memories are those that typically operate at the full processor
R 0xFFA1 0000 O
speed with little or no latency. At the L1 level, the instruction
INSTRUCTION SRAM (64K BYTES) M E 0xFFA0 0000
memory holds instructions only. The two data memories hold
M RESERVED L
data, and a dedicated scratchpad data memory stores stack and
A 0xFF90 8000 N DATA BANK B SRAM / CACHE (16K BYTES) R
local variable information.
E 0xFF90 4000 T DATA BANK B SRAM (16K BYTES) IN
In addition, multiple L1 memory blocks are provided, offering a
0xFF90 0000 RESERVED
configurable mix of SRAM and cache. The memory manage-
0xFF80 8000
ment Unit (MMU) provides memory protection for individual
DATA BANK A SRAM / CACHE (16K BYTES) 0xFF80 4000
tasks that may be operating on the core and can protect system
DATA BANK A SRAM (16K BYTES)
registers from unintended access.
0xFF80 0000 RESERVED
The architecture provides three modes of operation: user mode,
0xEF00 0000 RESERVED
supervisor mode, and emulation mode. User mode has
P 0x2040 0000 A ASYNC MEMORY BANK 3 (1M BYTES) OR M
restricted access to certain system resources, thus providing a
ON-CHIP FLASH (ADSP-BF538F8 ONLY) Y
protected software environment, while supervisor mode has
0x2030 0000 OR ASYNC MEMORY BANK 2 (1M BYTES) OR
unrestricted access to the system and core resources.
EM ON-CHIP FLASH (ADSP-BF538F8 ONLY) M 0x2020 0000 L
The Blackfin processor instruction set has been optimized so
ASYNC MEMORY BANK 1 (1M BYTES) OR A N ON-CHIP FLASH (ADSP-BF538F8 ONLY) R
that 16-bit opcodes represent the most frequently used instruc-
0x2010 0000 E
tions, resulting in excellent compiled code density. Complex
ASYNC MEMORY BANK 0 (1M BYTES) OR XT E ON-CHIP FLASH (ADSP-BF538F8 ONLY)
DSP instructions are encoded into 32-bit opcodes, representing
0x2000 0000 RESERVED
fully featured multifunction instructions. Blackfin processors
0x0800 0000 SDRAM MEMORY
support a limited multi-issue capability, where a 32-bit instruc-
(16M BYTES TO 128M BYTES)
tion can be issued in parallel with two 16-bit instructions,
0x0000 0000
allowing the programmer to use many of the core resources in a single instruction cycle. Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map The Blackfin processor assembly language uses an algebraic syn- The memory DMA controllers provide high bandwidth data tax for ease of coding and readability. The architecture has been movement capability. They can perform block transfers of code optimized for use in conjunction with the C/C++ compiler, or data between the internal memory and the external resulting in fast and efficient software implementations. memory spaces.
MEMORY ARCHITECTURE Internal (On-Chip) Memory
The ADSP-BF538/ADSP-BF538F processors view memory as a The ADSP-BF538/ADSP-BF538F processors have three blocks single unified 4G byte address space, using 32-bit addresses. All of on-chip memory, providing high bandwidth access to resources, including internal memory, external memory, and the core. I/O control registers, occupy separate sections of this common The first is the L1 instruction memory, consisting of 80K bytes address space. The memory portions of this address space are SRAM, of which 16K bytes can be configured as a four way arranged in a hierarchical structure to provide a good cost/per- set-associative cache. This memory is accessed at full formance balance of some very fast, low latency on-chip processor speed. memory as cache or SRAM, and larger, lower cost and perfor- mance off-chip memory systems. See Figure 3. The second on-chip memory block is the L1 data memory, con- sisting of two banks of up to 32K bytes each. Each memory bank The L1 memory system is the primary highest performance is configurable, offering both two-way set-associative cache and memory available to the Blackfin processor. The off-chip mem- SRAM functionality. This memory block is accessed at full pro- ory system, accessed through the External Bus Interface Unit cessor speed. (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of The third memory block is a 4K byte scratchpad SRAM, which physical memory. runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. Rev. E | Page 5 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide