Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 23

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ADSP-BF534/ADSP-BF536/ADSP-BF537 SPECIFICATIONS
Note that component specifications are subject to change without notice.
OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit
VDDINT Internal Supply Voltage1 Nonautomotive 300 MHz, 400 MHz, and 500 MHz speed 0.8 1.2 1.32 V grade models2 VDDINT Internal Supply Voltage1 Nonautomotive 533 MHz speed grade models2 0.8 1.25 1.375 V VDDINT Internal Supply Voltage1 Nonautomotive 600 MHz speed grade models2 0.8 1.3 1.43 V VDDINT Internal Supply Voltage1 Automotive grade models and +105°C nonautomotive 0.95 1.2 1.32 V grade models2 VDDEXT External Supply Voltage Nonautomotive grade models2 2.25 2.5 or 3.3 3.6 V VDDEXT External Supply Voltage Automotive grade models and +105°C nonautomotive 2.7 3.0 or 3.3 3.6 V grade models2 VDDRTC Real-Time Clock Power 2.25 3.6 V Supply Voltage VIH High Level Input Voltage3, 4 VDDEXT = Maximum 2.0 V VIHCLKIN High Level Input Voltage5 VDDEXT = Maximum 2.2 V VIH5V 5.0 V Tolerant Pins, High 0.7 × VDDEXT V Level Input Voltage6 VIH5V 5.0 V Tolerant Pins, High VDDEXT = Maximum 2.0 V Level Input Voltage7 VIL Low Level Input Voltage3, 8 VDDEXT = Minimum +0.6 V VIL5V 5.0 V Tolerant Pins, Low 0.3 × VDDEXT V Level Input Voltage6 VIL5V 5.0 V Tolerant Pins, Low VDDEXT = Minimum +0.8 V Level Input Voltage7 TJ Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40 +120 °C TAMBIENT = –40°C to +105°C TJ Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40 +105 °C TAMBIENT = –40°C to +85°C TJ Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ 0 +95 °C TAMBIENT = 0°C to +70°C TJ Junction Temperature 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40 +105 °C TAMBIENT = –40°C to +85°C TJ Junction Temperature 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ 0 +100 °C TAMBIENT = 0°C to +70°C 1 The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance. The required VDDINT is a function of speed grade and operating frequency. See Table 10, Table 11, and Table 12 for details. 2 See Ordering Guide on Page 67. 3 Bidirectional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) and input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF534/ADSP-BF536/ADSP-BF537 are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 4 Parameter value applies to all input and bidirectional pins except CLKIN, SDA, and SCL. 5 Parameter value applies to CLKIN pin only. 6 Applies to pins PJ2/SCL and PJ3/SDA which are 5.0 V tolerant (always accept up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 7 Applies to pin PJ4/DR0SEC/CANRX/TACI0 which is 5.0 V tolerant (always accepts up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 8 Parameter value applies to all input and bidirectional pins except SDA and SCL. Rev. J | Page 23 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide