Datasheet ADAU1702 (Analog Devices) - 5

Data Sheet ADAU1702 SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.
ANALOG PERFORMANCE
Specifications are guaranteed at 25°C (ambient).
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
ADC INPUTS Number of Channels 2 Stereo input Resolution 24 Bits Ful -Scale Input 100 (283) µA rms (µA p-p) 2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ internal) series resistor Signal-to-Noise Ratio A-Weighted 100 dB Dynamic Range −60 dB with respect to full-scale analog input A-Weighted 95 100 dB Total Harmonic Distortion + Noise −83 dB −3 dB with respect to full-scale analog input Interchannel Gain Mismatch 25 250 mdB Crosstalk −82 dB Analog channel-to-channel crosstalk DC Bias 1.4 1.5 1.6 V Gain Error −11 +11 % Group Delay 480 µs Delay is the same across all frequencies DAC OUTPUTS Number of Channels 4 Two stereo output channels Resolution 24 Bits Full-Scale Analog Output 0.9 (2.5) V rms (V p-p) Signal-to-Noise Ratio A-Weighted 104 dB Dynamic Range −60 dB with respect to full-scale analog output A-Weighted 99 104 dB Total Harmonic Distortion + Noise −90 dB −1 dB with respect to full-scale analog output Crosstalk −100 dB Analog channel-to-channel crosstalk Interchannel Gain Mismatch 25 250 mdB Gain Error −10 +10 % DC Bias 1.4 1.5 1.6 V Group Delay 400 µs Delay is the same across all frequencies VOLTAGE REFERENCE Absolute Voltage (CM) 1.4 1.5 1.6 V AUXILIARY ADC Full-Scale Analog Input 2.8 3.0 3.1 V INL 0.5 LSB DNL 1.0 LSB Offset 15 mV Input Impedance 17.8 30 42 kΩ Rev. D | Page 5 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE