Datasheet ADAU1702 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| Pages / Page | 52 / 7 — Data Sheet. ADAU1702. DIGITAL TIMING SPECIFICATIONS. Table 6. Digital … |
| Revision | D |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Data Sheet. ADAU1702. DIGITAL TIMING SPECIFICATIONS. Table 6. Digital Timing. Limit. Parameter. tMIN. tMAX. Unit. Description
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Data Sheet ADAU1702 DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 64).
Table 6. Digital Timing Limit Parameter tMIN tMAX Unit Description
MASTER CLOCK tMP 36 244 ns MCLKI period, 512 × fS mode tMP 48 366 ns MCLKI period, 384 × fS mode tMP 73 488 ns MCLKI period, 256 × fS mode tMP 291 1953 ns MCLKI period, 64 × fS mode SERIAL PORT tBIL 40 ns INPUT_BCLK (Pin 9) low pulse width tBIH 40 ns INPUT_BCLK (Pin 9) high pulse width tLIS 10 ns INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising tLIH 10 ns INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising tSIS 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to INPUT_BCLK (Pin 9) rising tSIH 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from INPUT_BCLK (Pin 9) rising tLOS 10 ns OUTPUT_LRCLK (Pin 16) setup in slave mode tLOH 10 ns OUTPUT_LRCLK (Pin 16) hold in slave mode tTS 5 ns OUTPUT_BCLK (Pin 19) fal ing to OUTPUT_LRCLK (Pin 16) timing skew tSODS 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time from OUTPUT_BCLK (Pin 19) falling tSODM 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode; time from OUTPUT_BCLK (Pin 19) falling SPI PORT fCCLK 6.25 MHz CCLK (Pin 23) frequency tCCPL 80 ns CCLK (Pin 23) pulse width low tCCPH 80 ns CCLK (Pin 23) pulse width high tCLS 0 ns CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising tCLH 100 ns CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising tCLPH 80 ns CLATCH (Pin 21) pulse width high tCDS 0 ns CDATA (Pin 20) setup; time to CCLK (Pin 23) rising tCDH 80 ns CDATA (Pin 20) hold; time from CCLK (Pin 23) rising tCOD 101 ns COUT (Pin 22) delay; time from CCLK (Pin 23) falling I2C PORT fSCL 400 kHz SCL (Pin 23) frequency tSCLH 0.6 µs SCL (Pin 23) high tSCLL 1.3 µs SCL (Pin 23) low tSCS 0.6 µs Setup time, relevant for repeated start condition tSCH 0.6 µs Hold time; after this period, the first clock is generated tDS 100 ns Data setup time tSCR 300 ns SCL (Pin 23) rise time tSCF 300 ns SCL (Pin 23) fall time tSDR 300 ns SDA (Pin 22) rise time tSDF 300 ns SDA (Pin 22) fall time tBFT 0.6 Bus-free time; time between stop and start MULTIPURPOSE PINS AND RESET tGRT 50 ns GPIO (MPx pins) rise time tGFT 50 ns GPIO (MPx pins) fall time tGIL 1.5 × 1/fS µs GPIO (MPx pins) input latency; time until high/low value is read by core tRLPW 20 ns RESET low pulse width Rev. D | Page 7 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADAU1702 DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 64).
Table 6. Digital Timing Limit Parameter tMIN tMAX Unit Description
MASTER CLOCK tMP 36 244 ns MCLKI period, 512 × fS mode tMP 48 366 ns MCLKI period, 384 × fS mode tMP 73 488 ns MCLKI period, 256 × fS mode tMP 291 1953 ns MCLKI period, 64 × fS mode SERIAL PORT tBIL 40 ns INPUT_BCLK (Pin 9) low pulse width tBIH 40 ns INPUT_BCLK (Pin 9) high pulse width tLIS 10 ns INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising tLIH 10 ns INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising tSIS 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to INPUT_BCLK (Pin 9) rising tSIH 10 ns SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from INPUT_BCLK (Pin 9) rising tLOS 10 ns OUTPUT_LRCLK (Pin 16) setup in slave mode tLOH 10 ns OUTPUT_LRCLK (Pin 16) hold in slave mode tTS 5 ns OUTPUT_BCLK (Pin 19) fal ing to OUTPUT_LRCLK (Pin 16) timing skew tSODS 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time from OUTPUT_BCLK (Pin 19) falling tSODM 40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode; time from OUTPUT_BCLK (Pin 19) falling SPI PORT fCCLK 6.25 MHz CCLK (Pin 23) frequency tCCPL 80 ns CCLK (Pin 23) pulse width low tCCPH 80 ns CCLK (Pin 23) pulse width high tCLS 0 ns CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising tCLH 100 ns CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising tCLPH 80 ns CLATCH (Pin 21) pulse width high tCDS 0 ns CDATA (Pin 20) setup; time to CCLK (Pin 23) rising tCDH 80 ns CDATA (Pin 20) hold; time from CCLK (Pin 23) rising tCOD 101 ns COUT (Pin 22) delay; time from CCLK (Pin 23) falling I2C PORT fSCL 400 kHz SCL (Pin 23) frequency tSCLH 0.6 µs SCL (Pin 23) high tSCLL 1.3 µs SCL (Pin 23) low tSCS 0.6 µs Setup time, relevant for repeated start condition tSCH 0.6 µs Hold time; after this period, the first clock is generated tDS 100 ns Data setup time tSCR 300 ns SCL (Pin 23) rise time tSCF 300 ns SCL (Pin 23) fall time tSDR 300 ns SDA (Pin 22) rise time tSDF 300 ns SDA (Pin 22) fall time tBFT 0.6 Bus-free time; time between stop and start MULTIPURPOSE PINS AND RESET tGRT 50 ns GPIO (MPx pins) rise time tGFT 50 ns GPIO (MPx pins) fall time tGIL 1.5 × 1/fS µs GPIO (MPx pins) input latency; time until high/low value is read by core tRLPW 20 ns RESET low pulse width Rev. D | Page 7 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
