Datasheet ADAU1701 (Analog Devices)

SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs Data Sheet ADAU1701 FEATURES GENERAL DESCRIPTION 28-/56-bit, 50 MIPS digital audio processor
The ADAU1701 is a complete single-chip audio system with a
2 ADCs: SNR of 100 dB, THD + N of −83 dB
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
4 DACs: SNR of 104 dB, THD + N of −90 dB
control interfaces. Signal processing includes equalization, cross-
Complete standalone operation
over, bass enhancement, multiband dynamics processing, delay
Self-boot from serial EEPROM
compensation, speaker compensation, and stereo image widening.
Auxiliary ADC with 4-input mux for analog control
This processing can be used to compensate for real-world
GPIOs for digital controls and outputs
limitations of speakers, amplifiers, and listening environments,
Fully programmable with SigmaStudio graphical tool
providing dramatic improvements in perceived audio quality.
28-bit × 28-bit multiplier with 56-bit accumulator for full
Its signal processing is comparable to that found in high end
double-precision processing
studio equipment. Most processing is done in full 56-bit, double
Clock oscillator for generating a master clock from crystal
precision mode, resulting in very good low level signal perfor-
PLL for generating master clock from 64 × fS, 256 × fS,
mance. The ADAU1701 is a fully programmable DSP. The easy to
384 × fS, or 512 × fS clocks
use SigmaStudio™ software al ows the user to graphical y configure
Flexible serial data input/output ports with I2S-compatible,
a custom signal processing flow using blocks such as biquad filters,
left-justified, right-justified, and TDM modes
dynamics processors, level controls, and GPIO interface controls.
Sampling rates of up to 192 kHz are supported On-chip voltage regulator for compatibility with 3.3 V systems
ADAU1701 programs can be loaded on power-up either from a
48-lead, plastic LQFP
serial EEPROM through its own self-boot mechanism or from an external microcontrol er. On power-down, the current state
APPLICATIONS
of the parameters can be written back to the EEPROM from the
Multimedia speaker systems
ADAU1701 to be recal ed the next time the program is run.
MP3 player speaker docks Automotive head units
Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog
Minicomponent stereos
input to analog output dynamic. Each ADC has a THD + N of
Digital televisions
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
Studio monitors
and output ports allow a glueless connection to additional
Speaker crossovers
ADCs and DACs. The ADAU1701 communicates through an
Musical instrument effects processors
I2C® bus or a 4-wire SPI port.
In-seat sound systems (aircraft/motor coaches) Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE