Datasheet AD5235 (Analog Devices) - 9

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Data Sheet AD5235 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK 1 16 RDY SDI 2 15 CS SDO 3 14 PR GND 4 AD5235 13 WP TOP VIEW VSS 5 12 VDD (Not to Scale) A1 6 11 A2 W1 7 10 W2 B1
005
8 9 B2
02816- Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. 3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 4 GND Ground Pin, Logic Ground Reference. 5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink 2 mA for 15 ms when storing data to EEMEM. 6 A1 Terminal A of RDAC1. 7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0. 8 B1 Terminal B of RDAC1. 9 B2 Terminal B of RDAC2. 10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1. 11 A2 Terminal A of RDAC2. 12 VDD Positive Power Supply. 13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe. CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used. 14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale until EEMEM is loaded with a new value by the user. PR is activated at the logic high transition. Tie PR to VDD, if not used. 15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. 16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and PR. Rev. F | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Electrical Characteristics—25 kΩ, 250 kΩ Versions Interface Timing and EEMEM Reliability Characteristics—25 kΩ, 250 kΩ Versions Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Scratchpad and EEMEM Programming Basic Operation EEMEM Protection Digital Input and Output Configuration Serial Data Interface Daisy-Chain Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Bypassing Advanced Control Modes Linear Increment and Decrement Instructions Logarithmic Taper Mode Adjustment Using to Re-Execute a Previous Command Using Additional Internal Nonvolatile EEMEM Calculating Actual End-to-End Terminal Resistance RDAC Structure Programming the Variable Resistor Rheostat Operation Programming the Potentiometer Divider Voltage Output Operation Programming Examples EVAL-AD5235SDZ Evaluation Kit Applications Information Bipolar Operation from Dual Supplies Gain Control Compensation High Voltage Operation DAC Bipolar Programmable Gain Amplifier 10-Bit Bipolar DAC Programmable Voltage Source with Boosted Output Programmable Current Source Programmable Bidirectional Current Source Programmable Low-Pass Filter Programmable Oscillator Optical Transmitter Calibration with ADN2841 Resistance Scaling Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations RDAC Circuit Simulation Model Outline Dimensions Ordering Guide