Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 9

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ADSP-21477 /ADSP-21478 /ADSP-21479 External Memory
Note that code execution is only supported from Bank 0 regard- less of VISA/ISA. Table 7 shows the address ranges for The external memory interface supports access to the external instruction fetch in each mode. memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be pro- grammed as either asynchronous or synchronous memory. The
Table 7. External Bank 0 Instruction Fetch
external ports are comprised of the following modules.
Size in
• An AMI which communicates with SRAM, FLASH, and
Access Type Words Address Range
other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external ISA (NW) 4M 0x0020 0000–0x005F FFFF memory in Bank 0 and 8M words of external memory in VISA (SW) 10M 0x0060 0000–0x00FF FFFF Bank 1, Bank 2, and Bank 3. • An SDRAM controller that supports a glueless interface
SDRAM Controller
with any of the standard SDRAMs. The SDC supports 62M words of external memory in Bank 0, and 64M words of The SDRAM controller, available on the ADSP-2147x in the external memory in Bank 1, Bank 2, and Bank 3. 196-ball CSP_BGA package, provides an interface of up to four • Arbitration logic to coordinate core and DMA transfers separate banks of industry-standard SDRAM devices or between internal and external memory over the DIMMs, at speeds up to fSDCLK. Fully compliant with the external port. SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between
External Port
4 Mbytes and 256 Mbytes of memory. SDRAM external mem- ory address space is shown in Table 8. The external port provides a high performance, glueless inter- face to a wide variety of industry-standard memory devices. The external port, available on the 196-ball CSP_BGA, may be used
Table 8. External Memory for SDRAM Addresses
to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory control-
Size in
lers. The first is an SDRAM controller for connection of
Bank Words Address Range
industry-standard synchronous DRAM devices while the sec- Bank 0 62M 0x0020 0000–0x03FF FFFF ond is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select Bank 1 64M 0x0400 0000–0x07FF FFFF pins enable up to four separate devices to coexist, supporting Bank 2 64M 0x0800 0000–0x0BFF FFFF any desired combination of synchronous and asynchronous Bank 3 64M 0x0C00 0000–0x0FFF FFFF device types. Non-SDRAM external memory address space is shown in Table 6. A set of programmable timing parameters is available to config-
Table 6. External Memory for Non-SDRAM Addresses
ure the SDRAM banks to support slower memory devices. The SDRAM and the AMI interface do not support 32-bit wide
Size in
devices.
Bank Words Address Range
The SDRAM controller address, data, clock, and control pins Bank 0 6M 0x0020 0000–0x007F FFFF can drive loads up to distributed 30 pF. For larger memory sys- Bank 1 8M 0x0400 0000–0x047F FFFF tems, the SDRAM controller external buffer timing should be Bank 2 8M 0x0800 0000–0x087F FFFF selected and external buffering should be provided so that the Bank 3 8M 0x0C00 0000–0x0C7F FFFF load on the SDRAM controller pins does not exceed 30 pF. Note that the external memory bank addresses shown are for
SIMD Access to External Memory
normal-word (32-bit) accesses. If 48-bit instructions as well as The SDRAM controller supports SIMD access on the 64-bit 32-bit data are both placed in the same external memory bank, external port data bus (EPD) which allows access to the comple- care must be taken while mapping them to avoid overlap. mentary registers on the PEy unit in the normal word space
Asynchronous Memory Controller
(NW). This improves performance since there is no need to explicitly load the complementary registers (as in SISD mode). The asynchronous memory controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides a con-
VISA and ISA Access to External Memory
figurable interface for up to four separate banks of memory or The SDRAM controller supports VISA code operation which I/O devices. Each bank can be independently programmed with reduces the memory load since the VISA instructions are com- different timing parameters, enabling connection to a wide vari- pressed. Moreover, bus fetching is reduced because, in the best ety of memory devices including SRAM, flash, and EPROM, as case, one 48-bit fetch contains three valid instructions. Code well as I/O devices that interface with standard memory control execution from the traditional ISA operation is also supported. lines. Bank 0 occupies a 6M word window and Banks 1, 2, and 3 Rev. D | Page 9 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide