Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 6

link to page 6 link to page 10
ADSP-21467/ ADSP-21469
Using the DM bus and PM buses, with one bus dedicated to a
ROM-Based Security
memory block, assures single-cycle execution with two data The ROM security feature provides hardware support for secur- transfers. In this case, the instruction must be available in the ing user software code by preventing unauthorized reading cache. from the internal code when enabled. When using this feature, The memory map in Table 3 displays the internal memory the processors do not boot-load any external code, executing address space of the processors. The 48-bit space section exclusively from internal ROM. Additionally, the processors are describes what this address range looks like to an instruction not freely accessible via the JTAG port. Instead, a unique 64-bit that retrieves 48-bit memory. The 32-bit section describes what key, which must be scanned in through the JTAG or Test Access this address range looks like to an instruction that retrieves 32- Port will be assigned to each customer. bit memory.
Digital Transmission Content Protection On-Chip Memory Bandwidth
The DTCP specification defines a cryptographic protocol for The internal memory architecture allows programs to have four protecting audio entertainment content from illegal copying, accesses at the same time to any of the four blocks (assuming intercepting, and tampering as it traverses high performance there are no block conflicts). The total bandwidth is realized digital buses, such as the IEEE 1394 standard. Only legitimate using the DMD and PMD buses (2 × 64-bits, CCLK speed) and entertainment content delivered to a source device via another the IOD0/1 buses (2 × 32-bit, PCLK speed). approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system.
Nonsecured ROM
For nonsecured ROM, booting modes are selected using the BOOTCFG pins as shown in Table 8 on Page 10. In this mode, emulation is always enabled, and the IVT is placed on the inter- nal RAM except for the case where BOOTCFGx = 011.
Table 3. Internal Memory Space1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 9000–0x0004 EFFF 0x0008 C000–0x0009 3FFF 0x0009 2000–0x0009 DFFF 0x0012 4000–0x0013 BFFF Reserved Reserved Reserved Reserved 0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 9000–0x0005 EFFF 0x000A C000–0x000B 3FFF 0x000B 2000–0x000B DFFF 0x0016 4000–0x0017 BFFF Reserved Reserved Reserved Reserved 0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 3FFF 0x000C 0000–0x000C 5554 0x000C 0000–0x000C 7FFF 0x0018 0000–0x0018 FFFF Reserved Reserved Reserved Reserved 0x0006 4000– 0x0006 FFFF 0x000C 5555–0x000D FFFF 0x000C 8000–0x000D FFFF 0x0019 0000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 3FFF 0x000E 0000–0x000E 5554 0x000E 0000–0x000E 7FFF 0x001C 0000–0x001C FFFF Reserved Reserved Reserved Reserved 0x0007 4000–0x0007 FFFF 0x000E 5555–0x0000F FFFF 0x000E 8000–0x000F FFFF 0x001D 0000–0x001F FFFF 1 Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales representative for additional details. Rev. B | Page 6 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide