Datasheet ADSP-21261, ADSP-21262, ADSP-21266 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | SHARC Embedded Processor |
| Pages / Page | 48 / 3 — ADSP-21261. /ADSP-21262. /ADSP-21266. GENERAL DESCRIPTION. Table 1. … |
| Revision | G |
| File Format / Size | PDF / 955 Kb |
| Document Language | English |
ADSP-21261. /ADSP-21262. /ADSP-21266. GENERAL DESCRIPTION. Table 1. Processor Benchmarks (at 200 MHz). Speed. Benchmark Algorithm
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ADSP-21261 /ADSP-21262 /ADSP-21266 GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs The ADSP-2126x continues the SHARC family’s industry-lead- are members of the SIMD SHARC family of DSPs featuring ing standards of integration for DSPs, combining a high Analog Devices, Inc., Super Harvard Architecture. The performance 32-bit DSP core with integrated, on-chip system ADSP-2126x is source code compatible with the ADSP-21160 features. These features include 2M bit dual-ported SRAM and ADSP-21161 DSPs as well as with first generation ADSP- memory, 4M bit dual-ported ROM, an I/O processor that sup- 2106x SHARC processors in SISD (single-instruction, single- ports 22 DMA channels, six serial ports, an SPI interface, data) mode. Like other SHARC DSPs, the ADSP-2126x are external parallel bus, and digital application interface. 32-bit/40-bit floating-point processors optimized for high per- The block diagram of the ADSP-2126x on Page 1 illustrates the formance audio applications with dual-ported on-chip SRAM, following architectural features: mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital application interface. • Two processing elements, each containing an ALU, multi- plier, shifter, and data register file Table 1 shows performance benchmarks for the processors run- ning at 200 MHz. Table 2 shows the features of the individual • Data address generators (DAG1, DAG2) product offerings. • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data
Table 1. Processor Benchmarks (at 200 MHz)
transfers between memory and the core at every core pro- cessor cycle
Speed Benchmark Algorithm (at 200 MHz)
• Three programmable interval timers with PWM genera- 1024 Point Complex FFT (Radix 4, with reversal) 61.3 s tion, PWM capture/pulse width measurement, and external event counter capabilities FIR Filter (per tap)1 3.3 ns IIR Filter (per biquad)1 13.3 ns • On-chip dual-ported SRAM (up to 2M bit) Matrix Multiply (pipelined) • On-chip dual-ported, mask-programmable ROM [3×3] × [3×1] 30 ns (up to 4M bit) [4×4] × [4×1] 53.3 ns • JTAG test access port Divide (y/x) 20 ns • 8- or 16-bit parallel port that supports interfaces to off-chip Inverse Square Root 30 ns memory peripherals 1 Assumes two files in multichannel SIMD mode. • DMA controller • Six full-duplex serial ports (four on the ADSP-21261) As shown in the functional block diagram in Figure 1 on Page 1, the ADSP-2126x uses two computational units to deliver a 5 to • SPI-compatible interface 10 times performance increase over previous SHARC proces- • Digital application interface that includes two precision sors on a range of DSP algorithms. Fabricated in a state-of-the- clock generators (PCG), an input data port (IDP), six serial art, high speed, CMOS process, the ADSP-2126x DSPs achieve ports, eight serial interfaces, a 20-bit synchronous parallel an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at input port, 10 interrupts, six flag outputs, six flag inputs, 150 MHz. With its SIMD computational hardware, the three programmable timers, and a flexible signal routing ADSP-2126x can perform 1200 MFLOPS running at 200 MHz, unit (SRU) or 900 MFLOPS running at 150 MHz.
FAMILY CORE ARCHITECTURE Table 2. ADSP-2126x SHARC Processor Features
The ADSP-2126x is code compatible at the assembly level with the ADSP-2136x and ADSP-2116x, and with the first generation
Feature ADSP-21261 ADSP-21262 ADSP-21266
ADSP-2106x SHARC DSPs. The ADSP-2126x shares architec- tural features with the ADSP-2136x and ADSP-2116x SIMD RAM 1M bit 2M bit 2M bit SHARC family of DSPs, as detailed in the following sections. ROM 3M bit 4M bit 4M bit
SIMD Computational Engine
Audio Decoders No No Yes in ROM1 The ADSP-2126x contain two computational processing ele- ments that operate as a single-instruction multiple-data (SIMD) DMA Channels 18 22 22 engine. The processing elements are referred to as PEX and PEY SPORTs 4 6 6 and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the Package 136-ball BGA 136-ball BGA 136-ball BGA PEYEN mode bit in the MODE1 register. When this mode is 144-lead LQFP 144-lead LQFP 144-lead LQFP enabled, the same instruction is executed in both processing 1 For information on available audio decoding algorithms, see Table 3 on Page 4. Rev. G | Page 3 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21261 /ADSP-21262 /ADSP-21266 GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs The ADSP-2126x continues the SHARC family’s industry-lead- are members of the SIMD SHARC family of DSPs featuring ing standards of integration for DSPs, combining a high Analog Devices, Inc., Super Harvard Architecture. The performance 32-bit DSP core with integrated, on-chip system ADSP-2126x is source code compatible with the ADSP-21160 features. These features include 2M bit dual-ported SRAM and ADSP-21161 DSPs as well as with first generation ADSP- memory, 4M bit dual-ported ROM, an I/O processor that sup- 2106x SHARC processors in SISD (single-instruction, single- ports 22 DMA channels, six serial ports, an SPI interface, data) mode. Like other SHARC DSPs, the ADSP-2126x are external parallel bus, and digital application interface. 32-bit/40-bit floating-point processors optimized for high per- The block diagram of the ADSP-2126x on Page 1 illustrates the formance audio applications with dual-ported on-chip SRAM, following architectural features: mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital application interface. • Two processing elements, each containing an ALU, multi- plier, shifter, and data register file Table 1 shows performance benchmarks for the processors run- ning at 200 MHz. Table 2 shows the features of the individual • Data address generators (DAG1, DAG2) product offerings. • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data
Table 1. Processor Benchmarks (at 200 MHz)
transfers between memory and the core at every core pro- cessor cycle
Speed Benchmark Algorithm (at 200 MHz)
• Three programmable interval timers with PWM genera- 1024 Point Complex FFT (Radix 4, with reversal) 61.3 s tion, PWM capture/pulse width measurement, and external event counter capabilities FIR Filter (per tap)1 3.3 ns IIR Filter (per biquad)1 13.3 ns • On-chip dual-ported SRAM (up to 2M bit) Matrix Multiply (pipelined) • On-chip dual-ported, mask-programmable ROM [3×3] × [3×1] 30 ns (up to 4M bit) [4×4] × [4×1] 53.3 ns • JTAG test access port Divide (y/x) 20 ns • 8- or 16-bit parallel port that supports interfaces to off-chip Inverse Square Root 30 ns memory peripherals 1 Assumes two files in multichannel SIMD mode. • DMA controller • Six full-duplex serial ports (four on the ADSP-21261) As shown in the functional block diagram in Figure 1 on Page 1, the ADSP-2126x uses two computational units to deliver a 5 to • SPI-compatible interface 10 times performance increase over previous SHARC proces- • Digital application interface that includes two precision sors on a range of DSP algorithms. Fabricated in a state-of-the- clock generators (PCG), an input data port (IDP), six serial art, high speed, CMOS process, the ADSP-2126x DSPs achieve ports, eight serial interfaces, a 20-bit synchronous parallel an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at input port, 10 interrupts, six flag outputs, six flag inputs, 150 MHz. With its SIMD computational hardware, the three programmable timers, and a flexible signal routing ADSP-2126x can perform 1200 MFLOPS running at 200 MHz, unit (SRU) or 900 MFLOPS running at 150 MHz.
FAMILY CORE ARCHITECTURE Table 2. ADSP-2126x SHARC Processor Features
The ADSP-2126x is code compatible at the assembly level with the ADSP-2136x and ADSP-2116x, and with the first generation
Feature ADSP-21261 ADSP-21262 ADSP-21266
ADSP-2106x SHARC DSPs. The ADSP-2126x shares architec- tural features with the ADSP-2136x and ADSP-2116x SIMD RAM 1M bit 2M bit 2M bit SHARC family of DSPs, as detailed in the following sections. ROM 3M bit 4M bit 4M bit
SIMD Computational Engine
Audio Decoders No No Yes in ROM1 The ADSP-2126x contain two computational processing ele- ments that operate as a single-instruction multiple-data (SIMD) DMA Channels 18 22 22 engine. The processing elements are referred to as PEX and PEY SPORTs 4 6 6 and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the Package 136-ball BGA 136-ball BGA 136-ball BGA PEYEN mode bit in the MODE1 register. When this mode is 144-lead LQFP 144-lead LQFP 144-lead LQFP enabled, the same instruction is executed in both processing 1 For information on available audio decoding algorithms, see Table 3 on Page 4. Rev. G | Page 3 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
