Datasheet Si8921/22 (Silicon Labs) - 7
| Manufacturer | Silicon Labs |
| Description | Isolated Amplifier for Current Shunt Measurement |
| Pages / Page | 30 / 7 — Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Timing. Note:. … |
| Revision | 0.5 |
| File Format / Size | PDF / 548 Kb |
| Document Language | English |
Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Timing. Note:. silabs.com
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Text Version of Document
link to page 7 Si8921/22 Data Sheet Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Units
Si8921A 70 77 dB Signal-to-Noise Si8921B 75 82 dB SNR Over 100 kHz Ratio Si8922A 64 71 dB Si8922B 69 76 dB Si8921A THD FIN = 1 kHz –85 –76 dB Total Harmonic Si8921B THD FIN = 1 kHz –88 –79 dB Distortion Si8922A THD FIN = 1 kHz –78 –69 dB Si8922B THD FIN = 1 kHz –81 –72 dB PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 –100 dB mV and 10 kHz ripple Power-Supply Rejection Ratio PSRR PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 –100 dB mV and 10 kHz ripple Between AON and AOP (Si8921) Output Resistive Load RLOAD 5 kΩ Between AO and GND (Si8922) Output Capacitive Load CLOAD Each pin to ground 100 pF
Timing
Signal Delay (Si8921) tPD 50% to 50% 0.8 µs Signal Delay (Si8922) tPD 50% to 50% 1 µs Rise Time tR 10% to 90% 0.8 µs Common-Mode Transient AIP = AIN = AGND, 50 75 kV/µs Immunity1 CMTI VCM = 1500 V
Note:
1. An analog CMTI failure is defined as an output error of more than 100 mV persisting for at least 1 µs.
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 7 Document Outline 1. Ordering Guide 2. System Overview 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 5.1 Si8921 Pin Descriptions 5.2 Si8922 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
Parameter Symbol Test Condition Min Typ Max Units
Si8921A 70 77 dB Signal-to-Noise Si8921B 75 82 dB SNR Over 100 kHz Ratio Si8922A 64 71 dB Si8922B 69 76 dB Si8921A THD FIN = 1 kHz –85 –76 dB Total Harmonic Si8921B THD FIN = 1 kHz –88 –79 dB Distortion Si8922A THD FIN = 1 kHz –78 –69 dB Si8922B THD FIN = 1 kHz –81 –72 dB PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 –100 dB mV and 10 kHz ripple Power-Supply Rejection Ratio PSRR PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 –100 dB mV and 10 kHz ripple Between AON and AOP (Si8921) Output Resistive Load RLOAD 5 kΩ Between AO and GND (Si8922) Output Capacitive Load CLOAD Each pin to ground 100 pF
Timing
Signal Delay (Si8921) tPD 50% to 50% 0.8 µs Signal Delay (Si8922) tPD 50% to 50% 1 µs Rise Time tR 10% to 90% 0.8 µs Common-Mode Transient AIP = AIN = AGND, 50 75 kV/µs Immunity1 CMTI VCM = 1500 V
Note:
1. An analog CMTI failure is defined as an output error of more than 100 mV persisting for at least 1 µs.
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 7 Document Outline 1. Ordering Guide 2. System Overview 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 5.1 Si8921 Pin Descriptions 5.2 Si8922 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
