Datasheet MxL7213 (MaxLinear) - 3
| Manufacturer | MaxLinear |
| Description | Dual 13A Power Module |
| Pages / Page | 4 / 3 — Figure 4: Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs. Figure 5: Pin … |
| File Format / Size | PDF / 554 Kb |
| Document Language | English |
Figure 4: Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs. Figure 5: Pin Configuration
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Text Version of Document
MxL7213 Dual 13A or Single 26A Power Module Product Brief Typical Application and Pin Configuration Typical Application INTVCC INTVCC RPGOOD1 CVCC 10kΩ 4.7μF PGOOD1 MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1 VIN VIN VOUT1 VOUT1 C1-C4 C C R1 R OUT1 OUT2 1.5V 13A TEMP TEMP VOUTS1 22μF CFF1(1) 100μF 470μF 10kΩ 25V 100kΩ RUN1 SW1 100pF Optional 6.3V 6.3V x2 RUN2 VFB1 TRACK1 VFB2 D1 R 5.1V Zener TRACK2 COMP1 FB2 R R C FB1 C COMP1(2) COMP1(2) FF2(1) Optional C 60.4kΩ SS1 FSET COMP2 40.2kΩ 100pF 0.1μF CSS2 R C PHASMD VOUTS2 COMP2(2) COMP2(2) VOUT2 0.1μF 1.2V 13A VOUT2 INTV C C SW2 CC OUT3 OUT4 100μF 470μF RSET PGOOD2 RPGOOD2 6.3V 6.3V 121kΩ SGND GND DIFFP DIFFN DIFFOUT 10kΩ x2 LOAD PGOOD2
Figure 4: Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs
Pin Configuration TEMP EXTVCC TEMP EXTVCC M M L L VIN VIN K K J J CLKOUT H INTVCC CLKOUT H INTVCC SW1 SW2 SW1 SW2 G G PGOOD1 PGOOD1 PHASMD RUN1 SGND PGOOD2 PHASMD RUN1 SGND PGOOD2 F RUN2 F RUN2 MODE_PLLIN DIFFOUT MODE_PLLIN GND COMP1 COMP2 GND COMP1 COMP2 DIFFOUT E DIFFP E DIFFP TRACK1 DIFFN DIFFN TRACK1 SGND VFB2 TRACK2 GND SGND VFB2 TRACK2 VFB1 VFB1 GND D D FSET SGND VOUTS2 FSET SGND VOUTS2 C C VOUTS1 VOUTS1 B B VOUT1 GND VOUT2 VOUT1 GND VOUT2 A A 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 LGA, Top View BGA, Top View 144-Lead 15mm x 15mm x 4.41mm 144-Lead 15mm x 15mm x 5.01mm
Figure 5: Pin Configuration
3/14/19 200PBR00 3 Document Outline General Description Applications Functional Block Diagram Typical Application Pin Configuration Ordering Information
Figure 4: Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs
Pin Configuration TEMP EXTVCC TEMP EXTVCC M M L L VIN VIN K K J J CLKOUT H INTVCC CLKOUT H INTVCC SW1 SW2 SW1 SW2 G G PGOOD1 PGOOD1 PHASMD RUN1 SGND PGOOD2 PHASMD RUN1 SGND PGOOD2 F RUN2 F RUN2 MODE_PLLIN DIFFOUT MODE_PLLIN GND COMP1 COMP2 GND COMP1 COMP2 DIFFOUT E DIFFP E DIFFP TRACK1 DIFFN DIFFN TRACK1 SGND VFB2 TRACK2 GND SGND VFB2 TRACK2 VFB1 VFB1 GND D D FSET SGND VOUTS2 FSET SGND VOUTS2 C C VOUTS1 VOUTS1 B B VOUT1 GND VOUT2 VOUT1 GND VOUT2 A A 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 LGA, Top View BGA, Top View 144-Lead 15mm x 15mm x 4.41mm 144-Lead 15mm x 15mm x 5.01mm
Figure 5: Pin Configuration
3/14/19 200PBR00 3 Document Outline General Description Applications Functional Block Diagram Typical Application Pin Configuration Ordering Information
