MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply Pin DescriptionPINNAMEFUNCTION 1 SCLK DAC Serial Clock Input 2 DIN DAC Serial Data Input 3 CL Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN. Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential 4 CS+ threshold is 2V. CS+ has typically 1MΩ resistance to ground. 5 CS- Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground. Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or 6 DACOUT sink 50µA. Feedback input. Connect to a resistive voltage-divider between the output voltage (V 7 FB OUT) and FB to set the output voltage. The feedback set point is 1.25V. Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is 8 COMP actively discharged to ground during shutdown or undervoltage conditions. 9 GND Ground 10 GATE Gate-Driver Output for External N-FET 11 VIN IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor. 12 CS DAC Chip-Select Input Detailed Description span and offset are independently settable with exter- nal resistors. See the Applications Information section Fixed Frequency PWM for output control equations. The MAX1932 uses a constant frequency, PWM, con- SPI Interface/Shutdown troller architecture. This controller sets the switch on- Use an SPI-compatible 3-wire serial interface with the time and drives an external N-channel MOSFET (see MAX1932 to control the DAC output voltage and to shut Figure 1). As the load varies, the error amplifier sets the down the MAX1932. Figures 4 and 5 show timing diagrams inductor peak current necessary to supply the load and for the SPI protocol. The MAX1932 is a write-only device regulate the output voltage. and uses CS along with SCLK and DIN to communicate. Output Current Limit The serial port is always operational when the device is The MAX1932 uses an external resistor at CS+ and CS- powered. To shut down the DC-DC converter portion only, to sense the output current (see Figure 2). The typical update the DAC registers to 00 hex. current-limit threshold is 2V. CL is designed to help find the optimum APD bias point by going low to indicate Applications Information when the APD reaches avalanche and that current limit Voltage Feedback Sense Point has been activated. To minimize noise, CL only Feedback can be taken from in front of, or after, the cur- changes state on an internal oscillator edge. rent-limit sense resistor. The current-limit sense resistor Output Control DAC forms a lowpass filter with the output capacitor. Taking An internal digital-to-analog converter can be used to feedback after the current-limit sense resistor (see Figure control the output voltage of the DC-DC converter 2), optimizes the output voltage accuracy, but requires (Figure 2). The DAC output is changed through an SPI™ overcompensation, which slows down the control loop serial interface using an 8-bit control byte. On power-up, response. For faster response, the feedback can be the DAC defaults to FF hex (1.25V), which corresponds taken from in front of the current-sense resistor (see to a minimum boost converter output voltage. Figure 3). This configuration however, makes the output voltage more sensitive to load variation and degrades Alternately, the output voltage can be set with external output accuracy by an amount equal to the load current resistors, an external DAC, or a voltage source. Output times the current-sense resistor value. SPI is a trademark of Motorola, Inc. www.maximintegrated.com Maxim Integrated | 6