Datasheet MA12070P (Infineon) - 5
| Manufacturer | Infineon |
| Description | 2x80W ultra power efficient, fully integrated audio amplifier IC with I2S digital input |
| Pages / Page | 88 / 5 — Table 4-1. Pin No. Name. Type1. Description. www.infineon.com |
| Revision | 01_00 |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
Table 4-1. Pin No. Name. Type1. Description. www.infineon.com
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Text Version of Document
4.2 Pin Function
Table 4-1 Pin No. Name Type1 Description
1 PVSS P Power ground for internal power amplifiers 2 PVSS P Power ground for internal power amplifiers 3 CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A 4 OUT0A O Audio power output 0A 5 OUT0A O Audio power output 0A 6 CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A 7 PVDD P Power supply for internal power amplifiers 8 PVDD P Power supply for internal power amplifiers 9 CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B 10 OUT0B O Audio power output 0B 11 OUT0B O Audio power output 0B 12 CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B 13 PVSS P Power ground for internal power amplifiers 14 PVSS P Power ground for internal power amplifiers 15 /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs 16 /ERROR O Error indicator (open drain output), pulled low when an error occurs 17 AVDD P Power supply for internal analog circuitry 18 CMSE O Decoupling pin for internally generated common-mode voltage in SE configuration. Should be externally decoupled to AVSS. Can be left floating for 2 x BTL and PBTL configurations. 19 AVSS P Ground for internal analog circuitry 20 CREF O Decoupling pin for internally generated analog reference voltage. Should be externally decoupled to AVSS. 21 SCK I I2S, digital audio serial clock. Must be synchronized to CLK 22 WS I I2S, digital audio word select. Must be synchronized to CLK 23 SD0 I I2S, digital audio serial data pair 0 24 SD1 I I2S, digital audio serial data pair 1 25 AVSS P Ground for internal analog circuitry 26 DVSS P Ground for internal digital circuitry 27 SCL IO I2C bus serial clock 28 AD0 I I2C device address select 0 (see “MCU/Serial control interface” section) 29 AD1 I I2C device address select 1 (see “MCU/Serial control interface” section) 30 SDA IO I2C bus serial data 31 CLKM/S I Reserved - must be pulled low 32 CLK I Clock input. Must be present before enabling the amplifier. 33 /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power consumption. 34 /MUTE I Mute audio output when pulled low 35 PVSS P Power ground for internal power amplifiers 36 PVSS P Power ground for internal power amplifiers 37 CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B 38 OUT1B O Audio power output 1B 39 OUT1B O Audio power output 1B 40 CF1BP P Connect to external flying capacitor positive terminal for amplifier channel 1B Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 5 of 88 2018-07-17
Table 4-1 Pin No. Name Type1 Description
1 PVSS P Power ground for internal power amplifiers 2 PVSS P Power ground for internal power amplifiers 3 CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A 4 OUT0A O Audio power output 0A 5 OUT0A O Audio power output 0A 6 CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A 7 PVDD P Power supply for internal power amplifiers 8 PVDD P Power supply for internal power amplifiers 9 CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B 10 OUT0B O Audio power output 0B 11 OUT0B O Audio power output 0B 12 CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B 13 PVSS P Power ground for internal power amplifiers 14 PVSS P Power ground for internal power amplifiers 15 /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs 16 /ERROR O Error indicator (open drain output), pulled low when an error occurs 17 AVDD P Power supply for internal analog circuitry 18 CMSE O Decoupling pin for internally generated common-mode voltage in SE configuration. Should be externally decoupled to AVSS. Can be left floating for 2 x BTL and PBTL configurations. 19 AVSS P Ground for internal analog circuitry 20 CREF O Decoupling pin for internally generated analog reference voltage. Should be externally decoupled to AVSS. 21 SCK I I2S, digital audio serial clock. Must be synchronized to CLK 22 WS I I2S, digital audio word select. Must be synchronized to CLK 23 SD0 I I2S, digital audio serial data pair 0 24 SD1 I I2S, digital audio serial data pair 1 25 AVSS P Ground for internal analog circuitry 26 DVSS P Ground for internal digital circuitry 27 SCL IO I2C bus serial clock 28 AD0 I I2C device address select 0 (see “MCU/Serial control interface” section) 29 AD1 I I2C device address select 1 (see “MCU/Serial control interface” section) 30 SDA IO I2C bus serial data 31 CLKM/S I Reserved - must be pulled low 32 CLK I Clock input. Must be present before enabling the amplifier. 33 /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power consumption. 34 /MUTE I Mute audio output when pulled low 35 PVSS P Power ground for internal power amplifiers 36 PVSS P Power ground for internal power amplifiers 37 CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B 38 OUT1B O Audio power output 1B 39 OUT1B O Audio power output 1B 40 CF1BP P Connect to external flying capacitor positive terminal for amplifier channel 1B Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 5 of 88 2018-07-17
