Datasheet STSPIN32F0B (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | Advanced single shunt BLDC controller with embedded STM32 MCU |
| Pages / Page | 36 / 4 — STSPIN32F0B. Block diagrams. Figure 3. Analog IC block diagram. 3.3V. … |
| File Format / Size | PDF / 6.5 Mb |
| Document Language | English |
STSPIN32F0B. Block diagrams. Figure 3. Analog IC block diagram. 3.3V. VREG12. ADJ REF. DS12907. Rev 1. page 4/36
Model Line for this Datasheet
Text Version of Document
STSPIN32F0B Block diagrams Figure 3. Analog IC block diagram
PA13_SWD_IO RESERVED RESERVED RESERVED V VR D D E _3V3 G VM S 12V W
3.3V VM VM
12V
VREG12 VREG12
VREG VBOOTU control
HS
HSU SWDIO_INT OUTU DC/DC Buck conv
VREG12
OC_TH_STBY1 OC comp threshold select 2 LSU
LS
OC_TH_STBY2 OC_COMP_INT2
VREG12
OC_SEL OC_SEL C VBOOTV HS3 G o HS2 6 at nt
HS
HSV HS1 e ro Driv LS3 l OUTV L LS2 o e gic
VREG12
LS1 r LSV
LS
OC_COMP_INT1
VREG12
VBOOTW
3.3V
HSW
HS
VDD OUTW TEST MODE
C VREG12 O O M P P AM
LSW
LS
GND
P ADJ REF
O O O O P P P 1O 1N 1P C Comp
DS12907
-
Rev 1 page 4/36
Document Outline 1 Description 2 Block diagrams 3 Electrical data 3.1 Absolute maximum ratings 3.2 ESD protections 3.3 Recommended operating conditions 3.4 Thermal data 4 Electrical characteristics 5 Pin description 6 Device description 6.1 UVLO and thermal protections 6.1.1 UVLO on supply voltages 6.1.2 Thermal protection 6.2 DC/DC buck regulator 6.2.1 External optional 3.3 V supply voltage 6.3 Linear regulator 6.4 Standby mode 6.5 Gate drivers 6.6 Microcontroller unit 6.6.1 Memories and boot mode 6.6.2 Power management 6.6.3 High-speed external clock source 6.6.4 Advanced-control timer (TIM1) 6.7 Test mode 6.8 Operational amplifier 6.9 Comparator 6.10 ESD protection strategy 7 Application example 8 Package information 8.1 VFQFPN48 7 x 7 package information Revision history Contents List of tables List of figures
PA13_SWD_IO RESERVED RESERVED RESERVED V VR D D E _3V3 G VM S 12V W
3.3V VM VM
12V
VREG12 VREG12
VREG VBOOTU control
HS
HSU SWDIO_INT OUTU DC/DC Buck conv
VREG12
OC_TH_STBY1 OC comp threshold select 2 LSU
LS
OC_TH_STBY2 OC_COMP_INT2
VREG12
OC_SEL OC_SEL C VBOOTV HS3 G o HS2 6 at nt
HS
HSV HS1 e ro Driv LS3 l OUTV L LS2 o e gic
VREG12
LS1 r LSV
LS
OC_COMP_INT1
VREG12
VBOOTW
3.3V
HSW
HS
VDD OUTW TEST MODE
C VREG12 O O M P P AM
LSW
LS
GND
P ADJ REF
O O O O P P P 1O 1N 1P C Comp
DS12907
-
Rev 1 page 4/36
Document Outline 1 Description 2 Block diagrams 3 Electrical data 3.1 Absolute maximum ratings 3.2 ESD protections 3.3 Recommended operating conditions 3.4 Thermal data 4 Electrical characteristics 5 Pin description 6 Device description 6.1 UVLO and thermal protections 6.1.1 UVLO on supply voltages 6.1.2 Thermal protection 6.2 DC/DC buck regulator 6.2.1 External optional 3.3 V supply voltage 6.3 Linear regulator 6.4 Standby mode 6.5 Gate drivers 6.6 Microcontroller unit 6.6.1 Memories and boot mode 6.6.2 Power management 6.6.3 High-speed external clock source 6.6.4 Advanced-control timer (TIM1) 6.7 Test mode 6.8 Operational amplifier 6.9 Comparator 6.10 ESD protection strategy 7 Application example 8 Package information 8.1 VFQFPN48 7 x 7 package information Revision history Contents List of tables List of figures
