link to page 6 link to page 6 link to page 6 link to page 6 STSPIN32F0BESD protections3.2ESD protectionsTable 2. ESD protection ratingsSymbolParameterTest conditionClassValueUnit Conforming to ANSI/ESDA/JEDEC HBM Human body model H2 2 kV JS-001-2014 Conforming to ANSI/ESDA/JEDEC CDM Charge device model C2 750 V JS-002-2014 3.3Recommended operating conditionsTable 3. Recommended operating conditionsSymbolParameterTest conditionMin.Typ.Max.Unit VM Power supply voltage - 6.7 (1) - 45 V dVM/dt Power supply voltage slope VM = 45 V - - 0.75 V/µs VDDA DC/DC regulator output voltage - - 3.3 - V LSW Output inductance - - 22 - µH CDDA Output capacitance - 47 - - µF ESRDDA Output capacitor ESR - - - 200 mΩ 13 < VM < 45 V - 12 - VREG12 Linear regulator output and gate driver supply voltage V Shorted to VM 6.7(1) - 15 CREG Load capacitance - 1 10 - µF ESRREG ESR load capacitance - - - 1.2 Ω VBO Floating supply voltage (2) - - VREG12 - 1 15 V VCP Comparator input voltage - 0 - 1 V Analog IC -40 - 125 °C Tj Operating junction temperature MCU (3) -40 - 125 °C 1. UVLO threshold VMOn_max. 2. VBO = VBOOT - VOUT. 3. See the STM32F031C6 datasheet (suffix 7 version). 3.4Thermal data Thermal values are calculated by simulation with the following boundary conditions: 2s2p board as per the std. JEDEC (JESD51-7) in natural convection, board dimensions: 114.3 x 76.2 x 1.6 mm, ambient temperature: 25 °C. Table 4. Thermal dataSymbolParameterValueUnit Rth (JA) Thermal resistance junction to ambient 45.6 °C/W DS12907 - Rev 1page 6/36 Document Outline 1 Description 2 Block diagrams 3 Electrical data 3.1 Absolute maximum ratings 3.2 ESD protections 3.3 Recommended operating conditions 3.4 Thermal data 4 Electrical characteristics 5 Pin description 6 Device description 6.1 UVLO and thermal protections 6.1.1 UVLO on supply voltages 6.1.2 Thermal protection 6.2 DC/DC buck regulator 6.2.1 External optional 3.3 V supply voltage 6.3 Linear regulator 6.4 Standby mode 6.5 Gate drivers 6.6 Microcontroller unit 6.6.1 Memories and boot mode 6.6.2 Power management 6.6.3 High-speed external clock source 6.6.4 Advanced-control timer (TIM1) 6.7 Test mode 6.8 Operational amplifier 6.9 Comparator 6.10 ESD protection strategy 7 Application example 8 Package information 8.1 VFQFPN48 7 x 7 package information Revision history Contents List of tables List of figures