Datasheet ADuM4137 (Analog Devices) - 4

ADuM4137 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND1, high-side voltages referenced to GND2, VDD1 = 12 V, VDD2 = 15 V, TJ = −40°C to +150°C, unless otherwise noted. Al minimum and maximum specifications apply over the entire recommended operating temperature range, unless otherwise noted. All typical specifications are at TJ = 25°C, VDD1 = 12 V, and VDD2 = 15 V, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS High-Side Power Supply Input Voltage, Secondary Side VDD2 12 25 V VDD2 Input Current, Quiescent IDD2 (Q) 9.8 11.5 16.0 mA TS1 = TS2 = open, VI+ = 0 V, VI− = 5 V, VDD2 = 25 V 12.8 15.2 20.0 mA TS1 = TS2 = 2 V, VI+ = 5 V, VI− = 0 V, VDD2 = 25 V V5_2 Regulated Output Voltage VV5_2 4.9 5.0 5.1 V Unloaded Logic Supply Input Voltage, Primary Side VDD1 4.5 25 V VDD1 Input Current IDD1 2.8 3.8 4.7 mA TS1 = TS2 = open, VI+ = 0 V, VI− = 5 V, TEMP_OUT floating, VDD1 = 4.5 V, VDD2 = 15 V 3.3 6.3 8.5 mA TS1 = TS2 = 2 V, VI+ = 5 V, VI− = 0 V, TEMP_OUT floating, VDD1 = 25 V, VDD2 = 15 V V5_1 Regulated Output Voltage VV5_1 4.9 5.0 5.1 V Unloaded Logic Inputs, VI+, VI−, CS, MOSI, SCLK Input Current (VI+, VI−, CS, MOSI, II −0.1 +0.01 +0.1 µA SCLK Only) Input Voltage Logic High VIH 2.5 V VDD1 ≥ 6 V 2.2 V 4.5 V ≤ VDD1 ≤ 6 V Logic Low Input Voltage VIL 0.9 V VDD1 ≥ 6 V 0.85 V 4.5 V ≤ VDD1 ≤ 6 V Logic Input Hysteresis VHYST 1.11 V VDD1 ≥ 6 V 1.02 V 4.5 V ≤ VDD1 ≤ 6 V UVLO_FAULT Logic High Input Voltage VIH_F 2.82 V VDD1 ≥ 6 V 2.56 V 4.5 V ≤ VDD1 ≤ 6 V Logic Low Input Voltage VIL_F 1.62 V VDD1 ≥ 6 V 1.46 V 4.5 V ≤ VDD1 ≤ 6 V Logic Input Hysteresis VHYS_F 0.93 V VDD1 ≥ 6 V 0.84 V 4.5 V ≤ VDD1 ≤ 6 V MISO Logic Output MISO N Channel Field Effect RDSON_MISO_N 9 20 Ω MISO current (IMISO) = 5 mA, VDD1 = 4.5 V Transistor (NFET) Drain to Source On Resistance (RDSON) MISO P Channel Field Effect RDSON_MISO_P 13 30 Ω IMISO = 5 mA, VDD1 = 4.5 V Transistor (PFET) RDSON MISO NFET High-Z Leakage IMISO_LK_N −0.1 +0.01 +0.1 µA MISO = 0 V MISO PFET High-Z Leakage IMISO_LK_P −0.1 +0.01 +0.1 µA MISO = 5 V Rev. 0 | Page 4 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bit LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit T_RAMP_OP Bit PWM_OSC CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit SPI SAFETY PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level Turn Off Miller Clamp Thermal Shutdown ASC Pin Functionality Isolated Temperature Sensor Low Temperature Operation Mode FAULTB Pin DRIVER_FAULTB Pin UVLO_FAULTB Pin VDD2 UVLO Fault UVLO_FAULTB Fault, Gate Low Dead Time Control DRIVER_FAULTB Fault, Dead Time Fault Power Dissipation INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS