Datasheet ADuM4122 (Analog Devices) - 4

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ADuM4122 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
VOUT_SRC PMOS Gate Resistance RDSON_P 1.4 3 Ω Tested at 250 mA, VDD2 = 15 V 1.4 3 Ω Tested at 500 mA, VDD2 = 15 V Peak Current IPK 2 A VDD2 = 12 V, 5 Ω gate resistance Short-Circuit Peak Current Minimum ISC_PK 3 A VDD2 = 5 V SWITCHING SPECIFICATIONS Pulse Width PW 50 ns VDD1 = 5 V, VDD2 = 15 V Propagation Delay2 ns Rising Edge tDLH 14 22 40 ns VDD1 = 5 V, VDD2 = 15 V Falling Edge tDHL 18 30 48 ns VDD1 = 5 V, VDD2 = 15 V Skew tPSK 36 ns Rising Edge tPSKLH 28 ns Falling Edge tPSKHL 30 ns Pulse Width Distortion tPWD 8 30 ns VDD1 = 5 V, VDD2 = 15 V Output Rise and Fall Time (20% to 80%) tR/tF 8 17 25 ns VDD1 = 5 V, VDD2 = 15 V, equivalent load capacitance (CL) = 2.2 nF, on path external series resistance (RGON) = off path external series resistance (RGOFF) = 4.7 Ω Required Time Before Next Edge tNE 100 ns VDD1 = 5 V, VDD2 = 15 V Common-Mode Transient Immunity (CMTI) |CM| Static CMTI3 150 kV/µs Common-mode voltage (VCM) = 1500 V Dynamic CMTI4 150 kV/µs VCM = 1500 V 1 NMOS means N-type metal-oxide semiconductor and PMOS means P-type metal-oxide semiconductor. 2 The tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 20% level of the VOUT signal or the VOUT_SRC signal. The tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 80% threshold of the VOUT signal or the VOUT_SRC signal. See Figure 29 for waveforms of propagation delay parameters. 3 The static CMTI is defined as the largest dV/dt between GND1 and GND2, with inputs held either high or low, such that the output voltage remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets. 4 The dynamic CMTI is defined as the largest dV/dt between GND1 and GND2, with the switching edge coincident with the transient test pulse. Operation with transients above the recommended levels can cause momentary data upsets.
REGULATORY INFORMATION
The ADuM4122 is pending approval by the organizations listed in Table 2.
Table 2. UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
UL1577 Component Approved under CSA Component Acceptance DIN V VDE V 0884-10 Certified under CQC11-471543- Recognition Program Notice 5A (VDE V 0884-10):2006-12 2012 Single Protection, 5000 V rms CSA 60950-1-07+A1+A2 and IEC 60950-1, Reinforced insulation, 849 V peak, GB4943.1-2011 Isolation Voltage second edition, +A1+A2: VIOSM = 10 kV peak Basic insulation at 800 V rms (1131 V peak) Basic insulation 849 V peak, VIOSM = Basic insulation at 800 V rms 16 kV peak (1131 V peak) Reinforced insulation at 400 V rms (565 V peak) Reinforced insulation at 400 V rms (565 V peak) IEC 60601-1 Edition 3.1: Basic insulation 1 means of patient protection (1 MOPP), 500 V rms (707 V peak) Reinforced insulation (2 MOPP), 250 V rms (1414 V peak) CSA 61010-1-12 and IEC 61010-1 third edition Basic insulation at: 600 V rms mains, 800 V secondary (1089 V peak) Reinforced insulation at: 300 V rms mains, 400 V secondary (565 V peak) File E214100 File 205078 File 2471900-4880-0001 File (pending) Rev. 0 | Page 4 of 18 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Electrical Specifications Regulatory Information Package Specifications Insulation and Safety Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Truth Table Typical Performance Characteristics Theory of Operation Applications Information PCB Layout Slew Rate Control Propagation Delay-Related Parameters Peak Current Rating Undervoltage Lockout Output Load Characteristics Power Dissipation Insulation Lifetime Typical Applications Outline Dimensions Ordering Guide