Datasheet ADuM4121/ADuM4121-1 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | High Voltage, Isolated Gate Driver with Internal Miller Clamp, 2 A Output |
| Pages / Page | 16 / 8 — ADuM4121/ADuM4121-1. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. … |
| File Format / Size | PDF / 535 Kb |
| Document Language | English |
ADuM4121/ADuM4121-1. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. VGATE. CH1 2.0V/DIV B
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ADuM4121/ADuM4121-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V V I– I+ 1 1 VGATE VGATE 2 2 CH1 2.0V/DIV B
-101
B
-104
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH1 2.0V/DIV W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH2 5.0V/DIV B B W: 1.0G 200ps/pt CH2 5.0V/DIV W: 1.0G 200ps/pt
14967 14967 Figure 4. VI+ to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor, Figure 7. VI− to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor, VDD2 = 15 V (VGATE Is the Voltage After a Gate Resistor) VDD2 = 15 V
VDD1 VI– 1 1 VGATE 2 VOUT 2 CH1 2.0V/DIV B
-102
B
-105
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH1 2.0V/DIV W: 1.0G A CH1 840mV 2.0µs/DIV 5.0GS/s CH2 5.0V/DIV B B W: 1.0G 200ps/pt CH2 5.0V/DIV W: 1.0G 200ps/pt
14967 14967 Figure 5. VI− to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor, Figure 8. Typical VDD1 Delay to Output Waveform, VI+ = VDD1, VI− = GND1 VDD2 = 15 V
5.0 VDD2 = 15V 4.5 VDD2 = 10V VDD2 = 5V V 4.0 I+ 1 3.5 VGATE 3.0 A) (m 2.5 I DD2 2.0 1.5 2 1.0 0.5 0 CH1 2.0V/DIV B
-103
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s 0 20 40 60 80 100
106
CH2 5.0V/DIV BW: 1.0G 200ps/pt
67- 14967
DUTY CYCLE (%)
149 Figure 6. VI+ to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor, Figure 9. IDD2 vs. Duty Cycle, VDD1 = 5 V, Switching Frequency (fSW) = 10 kHz, VDD2 = 15 V 2 nF Load Rev. 0| Page 8 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS REGULATORY INFORMATION PACKAGE CHARACTERISTICS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT VI+ and VI− Operation PROPAGATION DELAY-RELATED PARAMETERS UNDERVOLTAGE LOCKOUT (UVLO) OUTPUT LOAD CHARACTERISTICS Miller Clamp POWER DISSIPATION INSULATION LIFETIME TYPICAL APPLICATIONS OUTLINE DIMENSIONS ORDERING GUIDE
-101
B
-104
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH1 2.0V/DIV W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH2 5.0V/DIV B B W: 1.0G 200ps/pt CH2 5.0V/DIV W: 1.0G 200ps/pt
14967 14967 Figure 4. VI+ to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor, Figure 7. VI− to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor, VDD2 = 15 V (VGATE Is the Voltage After a Gate Resistor) VDD2 = 15 V
VDD1 VI– 1 1 VGATE 2 VOUT 2 CH1 2.0V/DIV B
-102
B
-105
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s CH1 2.0V/DIV W: 1.0G A CH1 840mV 2.0µs/DIV 5.0GS/s CH2 5.0V/DIV B B W: 1.0G 200ps/pt CH2 5.0V/DIV W: 1.0G 200ps/pt
14967 14967 Figure 5. VI− to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor, Figure 8. Typical VDD1 Delay to Output Waveform, VI+ = VDD1, VI− = GND1 VDD2 = 15 V
5.0 VDD2 = 15V 4.5 VDD2 = 10V VDD2 = 5V V 4.0 I+ 1 3.5 VGATE 3.0 A) (m 2.5 I DD2 2.0 1.5 2 1.0 0.5 0 CH1 2.0V/DIV B
-103
W: 1.0G A CH1 840mV 40.0ns/DIV 5.0GS/s 0 20 40 60 80 100
106
CH2 5.0V/DIV BW: 1.0G 200ps/pt
67- 14967
DUTY CYCLE (%)
149 Figure 6. VI+ to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor, Figure 9. IDD2 vs. Duty Cycle, VDD1 = 5 V, Switching Frequency (fSW) = 10 kHz, VDD2 = 15 V 2 nF Load Rev. 0| Page 8 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS REGULATORY INFORMATION PACKAGE CHARACTERISTICS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT VI+ and VI− Operation PROPAGATION DELAY-RELATED PARAMETERS UNDERVOLTAGE LOCKOUT (UVLO) OUTPUT LOAD CHARACTERISTICS Miller Clamp POWER DISSIPATION INSULATION LIFETIME TYPICAL APPLICATIONS OUTLINE DIMENSIONS ORDERING GUIDE
