Datasheet A3955 (Allegro) - 2
| Manufacturer | Allegro |
| Description | Full-Bridge PWM Microstepping Motor Driver |
| Pages / Page | 14 / 2 — A3955. Full-Bridge PWM Microstepping Motor Driver. Features and Benefits. … |
| File Format / Size | PDF / 513 Kb |
| Document Language | English |
A3955. Full-Bridge PWM Microstepping Motor Driver. Features and Benefits. Description. Packages:. Functional Block Diagram
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A3955 Full-Bridge PWM Microstepping Motor Driver Features and Benefits Description
▪ ±1.5 A continuous output current The A3955 is designed to drive one winding of a bipolar ▪ 50 V output voltage rating stepper motor in a microstepping mode. The outputs are ▪ Internal PWM current control rated for continuous output currents to ±1.5 A and operating ▪ 3-bit nonlinear DAC voltages to 50 V. Internal pulse width modulated (PWM) current ▪ Fast, mixed fast/slow, and slow current-decay modes control combined with an internal three-bit nonlinear digital- ▪ Internal transient-suppression diodes to-analog converter allows the motor current to be controlled ▪ Internal thermal shutdown circuitry in full-, half-, quarter-, or eighth-step (microstepping) modes. ▪ Crossover-current and UVLO protection Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance problems at low speed. Internal circuitry determines whether the PWM current-control circuitry operates in a slow (recirculating) current-decay
Packages:
mode, fast (regenerative) current-decay mode, or in a mixed current-decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, Package B, 16-pin DIP Package LB, 16-pin SOIC digitally selected output current ratio; and slow, fast, or mixed with exposed tabs with internally fused pins current-decay modes provides users with a broad, variable range of motor control. Not to scale Continued on the next page…
Functional Block Diagram
A B LOGIC SUPPLY OUT OUT LOAD SUPPLY 6 10 15 16 PHASE VCC 7 VBB GROUND 4 5 UVLO 12 & TSD 13 BLANKING CURRENT-SENSE SENSE MIXED-DECAY PWM LATCH GATE COMPARATOR 11 COMPARATOR + PFD 1 + R – – Q S BLANKING ÷3 D/A DISABLE R V + – S CC RC VTH 3 2 8 9 14 2 1 0 D D D REF CT RT Dwg. FP-042 29319.41G
▪ ±1.5 A continuous output current The A3955 is designed to drive one winding of a bipolar ▪ 50 V output voltage rating stepper motor in a microstepping mode. The outputs are ▪ Internal PWM current control rated for continuous output currents to ±1.5 A and operating ▪ 3-bit nonlinear DAC voltages to 50 V. Internal pulse width modulated (PWM) current ▪ Fast, mixed fast/slow, and slow current-decay modes control combined with an internal three-bit nonlinear digital- ▪ Internal transient-suppression diodes to-analog converter allows the motor current to be controlled ▪ Internal thermal shutdown circuitry in full-, half-, quarter-, or eighth-step (microstepping) modes. ▪ Crossover-current and UVLO protection Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance problems at low speed. Internal circuitry determines whether the PWM current-control circuitry operates in a slow (recirculating) current-decay
Packages:
mode, fast (regenerative) current-decay mode, or in a mixed current-decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, Package B, 16-pin DIP Package LB, 16-pin SOIC digitally selected output current ratio; and slow, fast, or mixed with exposed tabs with internally fused pins current-decay modes provides users with a broad, variable range of motor control. Not to scale Continued on the next page…
Functional Block Diagram
A B LOGIC SUPPLY OUT OUT LOAD SUPPLY 6 10 15 16 PHASE VCC 7 VBB GROUND 4 5 UVLO 12 & TSD 13 BLANKING CURRENT-SENSE SENSE MIXED-DECAY PWM LATCH GATE COMPARATOR 11 COMPARATOR + PFD 1 + R – – Q S BLANKING ÷3 D/A DISABLE R V + – S CC RC VTH 3 2 8 9 14 2 1 0 D D D REF CT RT Dwg. FP-042 29319.41G
