Datasheet AD7768-1 (Analog Devices) - 3

link to page 79 link to page 79 link to page 80 link to page 80
Data Sheet AD7768-1
Coefficient Data Register ... 79  Ordering Guide ... 80  Access Key Register ... 79  Outline Dimensions .. 80 
REVISION HISTORY 5/2019—Rev. 0 to Rev. A
Changes to Single-Supply Mode Section, Recommended Power Changes to Features .. 1 Supply Configuration Section, and Figure 79 ... 43 Changes to General Description Section ... 4 Added Figure 80 .. 43 Change to Test Conditions/Comments for Spurious-Free Changes to Synchronization of Multiple AD7768-1 Devices Dynamic Range (SFDR) Parameters, Table 1 ... 5 section and Figure 95 .. 57 Change to Test Conditions/Comments for SFDR Parameter, Change to Recommended Driver Amplifiers Section and Table 2 ... 10 Table 25 ... 59 Changes to Note 1, Figure 9 ... 18 Change to Reg (Hex) 14, Bit 7, Table 31 and Reg (Hex) 29, Changes to Table 7 .. 19 Bit 3, Table 31 ... 66 Changes to Figure 52 .. 27 Change to Reg (Hex) 2F, Bit 3, Table 31 ... 67 Added Figure 55 and Figure 56; Renumbered Sequentially .. 27 Changes to Bit 2 Description, Table 39 .. 69 Changes to Terminology Section .. 28 Changes to Bits[6:4] Description, Table 44 ... 72 Changes to Noise Performance and Resolution Section .. 30 Changes to Bit 7, Access, Table 48 and Bit 7, Description, Changes to Table 10 and Table 11 ... 31 Table 49 ... 74 Changes to ADC Core and Signal Chain Section ... 32 Changes to Bit 3, Description, Table 58 and Bit 3, Bit Name and Changes to Figure 67, Figure 68, and Clocking and Clock Description, Table 59 .. 77 Selection Section ... 35 Changes to Bit 3, Bit Name and Description, Table 64 .. 78 Changes to Sinc3 Filter Section ... 37 Update Outline Dimensions .. 80 Changes to Figure 77 .. 41
5/2018—Revision 0: Initial Version
Rev. A | Page 3 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE