Datasheet AD7691-EP (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR® Differential ADC in MSOP/QFN |
| Pages / Page | 13 / 8 — AD7691-EP. Enhanced Product. PIN CONFIGURATIONS AND FUNCTION … |
| Revision | A |
| File Format / Size | PDF / 444 Kb |
| Document Language | English |
AD7691-EP. Enhanced Product. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. REF. 10 VIO. VDD. SDI. IN+. SCK. TOP VIEW. IN–. (Not to Scale). SDO
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AD7691-EP Enhanced Product PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI AD7691-EP IN+ 3 8 SCK TOP VIEW IN– 4 (Not to Scale) 7 SDO
004
GND 5 6 CNV
12156- Figure 5. 10-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple this pin closely with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and VREF, centered about VREF/2 and must be driven 180° out of phase with IN−. 4 IN− AI Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and VREF, centered about VREF/2 and must be driven 180° out of phase with IN+. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device, either chain mode or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 8 of 13 Document Outline Features Enhanced Product Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
004
GND 5 6 CNV
12156- Figure 5. 10-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple this pin closely with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and VREF, centered about VREF/2 and must be driven 180° out of phase with IN−. 4 IN− AI Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and VREF, centered about VREF/2 and must be driven 180° out of phase with IN+. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device, either chain mode or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 8 of 13 Document Outline Features Enhanced Product Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
