Datasheet AD7466-KGD (Analog Devices) - 8

AD7466-KGD Known Good Die PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 6 2 5 3 4
04 0 315- 10 Figure 4. Pad Configuration
Table 4. Pad Function Descriptions Pad No. X-Axis (μm) Y-Axis (μm) Mnemonic Pad Type Description
1 −173 +634 CS Single Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the devices and frames the serial data transfer. 2 −173 +494 SDATA Single Data Out. Logic output. The conversion result from the AD7466-KGD is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7466-KGD consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. 3 −187 −600 SCLK Single Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the parts. This clock input is also used as the clock source for the conversion process of the parts. 4 +187 −600 VIN Single Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. 5A +173 +447.6 GND Double Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should be referred to this GND voltage. 5B +173 +489.6 GND Double Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should be referred to this GND voltage. 6A +173 +637.6 VDD Double Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V. 6B +173 +679.6 VDD Double Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V. Rev. A | Page 8 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE