Datasheet AD9690 (Analog Devices) - 4

AD9690 Data Sheet GENERAL DESCRIPTION
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital The programmable threshold detector allows monitoring of the converter (ADC). The device has an on-chip buffer and sample- incoming signal power using the fast detect output bits of the and-hold circuit designed for low power, small size, and ease of ADC. If the input signal level exceeds the programmable use. This device is designed for sampling wide bandwidth threshold, the fast detect indicator goes high. Because this analog signals of up to 2 GHz. The AD9690 is optimized for threshold indicator has low latency, the user can quickly turn wide input bandwidth, high sampling rate, excel ent linearity, down the system gain to avoid an overrange condition at the and low power in a small package. ADC input. The ADC core features a multistage, differential pipelined Users can configure the Subclass 1 JESD204B-based high speed architecture with integrated output error correction logic. The serialized output in a variety of one-, two-, or four-lane con- ADC features wide bandwidth inputs supporting a variety of figurations, depending on the DDC configuration and the user-selectable input ranges. An integrated voltage reference acceptable lane rate of the receiving logic device. Multiple device eases design considerations. synchronization is supported through the SYSREF± and The analog input and clock signals are differential inputs. The SYNCINB± input pins. ADC data output is internally connected to two digital down- The AD9690 has flexible power-down options that al ow converters (DDCs). Each DDC consists of four cascaded signal significant power savings when desired. All of these features can processing stages: a 12-bit frequency translator (NCO), and four be programmed using a 1.8 V to 3.3 V capable 3-wire SPI. half-band decimation filters. The AD9690 is available in a Pb-free, 64-lead LFCSP and is In addition to the DDC blocks, the AD9690 has several specified over the −40°C to +85°C industrial temperature range. functions that simplify the automatic gain control (AGC) This product may be protected by one or more U.S. or international function in the communications receiver. patents Rev. B | Page 4 of 78 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9690-1000 AD9690-500 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing Voltage Reference Clock Input Considerations Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC Overrange and Fast Detect ADC Overrange Fast Threshold Detection (FD) Signal Monitor SPORT Over JESD204B Digital Downconverter (DDC) DDC I/Q Input Selection DDC I/Q Output Selection DDC General Description Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Plus Mixer Loss and SFDR Numerically Controlled Oscillator Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR Filters General Description Half-Band Filters HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC Gain Stage DDC Complex—Real Conversion DDC Example Configurations Digital Outputs Introduction to the JESD204B Interface JESD204B Overview Functional Overview Transport Layer Data Link Layer Physical Layer JESD204B Link Establishment Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder Physical Layer (Driver) Outputs Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B Tx Converter Mapping Configuring the JESD204B Link Multichip Synchronization SYSREF± Setup/Hold Window Monitor Test Modes ADC Test Modes JESD204B Block Test Modes Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes Serial Port Interface Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels SPI Soft Reset Memory Map Register Table Applications Information Power Supply Recommendations Exposed Pad Thermal Heat Slug Recommendations AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) Outline Dimensions Ordering Guide