Datasheet AD9234 (Analog Devices) - 4

AD9234 Data Sheet GENERAL DESCRIPTION
The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The down the system gain to avoid an overrange condition at the device has an on-chip buffer and sample-and-hold circuit ADC input. In addition to the fast detect outputs, the AD9234 designed for low power, small size, and ease of use. This also offers signal monitoring capability. The signal monitoring product is designed for sampling wide bandwidth analog block provides additional information about the signal being signals. The AD9234 is optimized for wide input bandwidth, digitized by the ADC. high sampling rate, excellent linearity, and low power in a small Users can configure the Subclass 1 JESD204B-based high speed package. serialized output in a variety of one-, two-, or four-lane The dual ADC cores feature a multistage, differential pipelined configurations, depending on the acceptable lane rate of the architecture with integrated output error correction logic. Each receiving logic device and the sampling rate of the ADC. ADC features wide bandwidth buffered inputs supporting a Multiple device synchronization is supported through the variety of user-selectable input ranges. An integrated voltage SYSREF± and SYNCINB± input pins. reference eases design considerations. Each ADC data output is The AD9234 has flexible power-down options that allow internal y connected to an optional decimate by 2 block. significant power savings when desired. All of these features The AD9234 has several functions that simplify the automatic can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI. gain control (AGC) function in a communications receiver. The AD9234 is available in a Pb-free, 64-lead LFCSP and is The programmable threshold detector allows monitoring of specified over the −40°C to +85°C industrial temperature range. the incoming signal power using the fast detect output bits of This product is protected by a U.S. patent. the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn Rev. B | Page 4 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE