Datasheet AD9675 (Analog Devices) - 41

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Data Sheet AD9675 RF DECIMATOR 2 1
The input to the RF decimator is either the ADC output data or a test waveform, as described in the Digital Test Waveforms
0
section. The test waveforms are enabled per channel using
) –1 S LOW BAND FILTER
Address 0x11A (see Table 31).
HIGH BAND FILTER BF –2 (d E DC Offset Calibration –3 UD IT
The user can reduce dc offset through a manual system
L P –4
calibration process. Measure the dc offset of every channel in
AM –5
the system and then set a calibration value using Address 0x110
–6
and Address 0x111. Note that these registers are both chip and
–7
local addresses, meaning that they are accessed using the chip address and device index. Bypass the dc offset calibration using
–8
5
0 2 4 6 8 10 12 14 16 18 20
05 Address 0x10F, Bits[2:0].
FREQUENCY (MHz)
381- 1 1
Multiband AAF and Decimate by 2
Figure 58. AAF Frequency Response, Zoomed In (Frequency Scale Assumes fADC = 2 × fDEC = 40 MHz) The multiband filter is an FIR filter. It is programmable with low or
High-Pass Filter
high bandwidth filtering. The filter requires 11 input samples to populate the filter. The decimation rate is fixed at 2×. Therefore, The user can apply a second-order Butterworth high-pass IIR the decimation frequency is f filter after the RF decimator. The filter has a cutoff of 700 kHz DEC = fSAMPLE/2. Figure 57 and Figure 58 show the frequency response of the filter, depending for an encode clock of 50 MHz. The filter has a settling time of on the mode. Figure 57 shows the attenuation amplitude over 2.5 μs. Therefore, if the ADC clock is 50 MHz, ignore the first the Nyquist frequency range. Figure 58 shows the pass band 125 samples (2.5 μs/0.02 μs). Bypass or enable the filter in the response as nearly flat. vector profile if the filter is enabled in Register 0x113, Bit 5. If the filter is bypassed by setting Register 0x113, Bit 5 to 1, the
10
filter cannot be enabled from the vector profile.
0 DIGITAL TEST WAVEFORMS LOW BAND FILTER HIGH BAND FILTER ) –10
Digital test waveforms can be used in the digital processing block
S BF
instead of the ADC output. To enable digital test waveforms,
(d –20 E
use Address 0x11B. Enable each channel individually in
UD
Address 0x11A.
IT L –30 P Waveform Generator AM –40
For testing and debugging, use a programmable waveform
–50
generator in place of ADC data. The waveform generator can vary offset, amplitude, and frequency. The generator uses the
–60
ADC sample frequency, fSAMPLE, and ADC full-scale amplitude,
0 2 4 6 8 10 12 14 16 18 20
054 81-
FREQUENCY (MHz)
13 A 1 FULL-SCALE, as references. The values are set in Address 0x117, Figure 57. AAF Frequency Response (Frequency Scale Assumes Address 0x118, and Address 0x119 (see Table 31). fADC = 2 × fDEC = 40 MHz) x = C + A × sin(2 × π × N) (8) f n N SAMPLE  , see Address 0x117 (9) 64 AFULLSCALE A  , see Address 0x118 (10) x 2 C = AFULL-SCALE × a × 2−(13 − b), see Address 0x119 (11)
Channel ID and Ramp Generator
In Channel ID test mode, the output is a concatenated value. Bits[6:0] are a ramp. Bit 7 is reserved as 0. Bits[10:8] are the channel ID such that Channel A is coded as 000 and Channel B is 001. Bits[15:11] are the chip address. Rev. A | Page 41 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide