Datasheet AD9671 (Analog Devices) - 6

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AD9671 Data Sheet Parameter1 Test Conditions/Comments Min Typ Max Unit
Noise Figure RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB 5.7 dB LNA gain = 17.9 dB 4.5 dB LNA gain = 21.6 dB 3.4 dB Input Referred Dynamic Range RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 164 dBFS/√Hz LNA gain = 17.9 dB 162 dBFS/√Hz LNA gain = 21.6 dB 160 dBFS/√Hz Close-In SNR −3 dBFS input, fRF = 2.5 MHz, fLO = 156 dBc/√Hz 40 MHz, 1 kHz offset, 16LO mode, one channel enabled −3 dBFS input, fRF = 2.5 MHz, fLO = 161 dBc/√Hz 40 MHz, 1 kHz offset, 16LO mode, eight channels enabled Two-Tone Intermodulation fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = −58 dBc Distortion (IMD3) 80 MHz, ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 LO Harmonic Rejection −20 dBc Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel to Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY Mode I/Mode II/Mode III/Mode IV AVDD1 1.7 1.8 1.9 V AVDD2 2.85 3.0 3.6 V DVDD Demodulator/decimator enabled 1.3 1.4 1.9 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode, low bandwidth mode 148/187/223/291 mA CW Doppler mode 4 mA IAVDD2 TGC mode, no signal, low bandwidth 230 mA mode TGC mode, no signal, high 239 mA bandwidth mode CW Doppler mode 140 mA IDVDD Demodulator/decimator enabled 156/247/166/255 mA Demodulator/decimator disabled 29/46/40/61 mA IDRVDD Four-lane mode, JESD204B lane rates = 121/168/122/166 mA 1.6 Gbps/2.6 Gbps/1.6 Gbps/2.5 Gbps Two-lane mode, JESD204B lane rates = 127/186/129/184 mA 3.2 Gbps/5.0 Gbps/3.2 Gbps/5.0 Gbps One-lane mode, demodulator/ 73/105/76/105 mA decimator enabled, JESD204B lane rates = 3.2 Gbps/5.0 Gbps/3.2 Gbps/ 5.0 Gbps 4 Total Power Dissipation TGC mode, no signal, two-lane mode, 1200/1415/1365/1615 1445/1680/1635/ mW (Including Output Drivers) demodulator/decimator disabled 1910 TGC mode, no signal, two-lane mode, 1390/1710/1550/1895 1645/2025/1835/ mW demodulator/decimator enabled 2215 CW Doppler mode, eight channels 500 mW enabled Power-Down Dissipation 5 30 mW Standby Power Dissipation 725 mW Rev. A| Page 6 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control DIGITAL OUTPUTS AND TIMING JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Verify FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Super Frame and Output Zero Stuffing Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins ANALOG TEST TONE GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Update (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE