Datasheet AD8284 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Radar Receive Path AFE: 4-Channel MUX with LNA, PGA, AAF, and ADC |
| Pages / Page | 28 / 6 — AD8284. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter. Symbol. … |
| Revision | D |
| File Format / Size | PDF / 640 Kb |
| Document Language | English |
AD8284. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter. Symbol. Temperature. Min. Typ. Max. Unit. Timing and Switching Diagram
Model Line for this Datasheet
Text Version of Document
AD8284 Data Sheet SWITCHING SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. All specifications guaranteed by design only.
Table 4. Parameter
1
Symbol Temperature Min Typ Max Unit
CLOCK Clock Rate Full 10 60 MSPS Clock Pulse Width High at 60 MSPS tEH Full 8.33 ns Clock Pulse Width Low at 60 MSPS tEL Full 8.33 ns Clock Pulse Width High at 40 MSPS tEH Full 12.5 ns Clock Pulse Width Low at 40 MSPS tEL Full 12.5 ns OUTPUT PARAMETERS Propagation Delay at 60 MSPS tPD Full 6 ns Rise Time tR Full 1.9 ns Fall Time tF Full 1.2 ns Data Setup Time at 60 MSPS tDS Full 8.33 ns Data Hold Time at 60 MSPS tDH Full 6.0 ns Data Setup Time at 40 MSPS tDS Full 18 ns Data Hold Time at 40 MSPS tDH Full 6 ns Pipeline Latency Full 7 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology.
Timing and Switching Diagram N N –1 INAx tEH tEL CLK– CLK+ t t t PD DS DH D11 to D0 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
002 992- 10 Figure 2. Timing Definitions for Switching Specifications Rev. D | Page 6 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. All specifications guaranteed by design only.
Table 4. Parameter
1
Symbol Temperature Min Typ Max Unit
CLOCK Clock Rate Full 10 60 MSPS Clock Pulse Width High at 60 MSPS tEH Full 8.33 ns Clock Pulse Width Low at 60 MSPS tEL Full 8.33 ns Clock Pulse Width High at 40 MSPS tEH Full 12.5 ns Clock Pulse Width Low at 40 MSPS tEL Full 12.5 ns OUTPUT PARAMETERS Propagation Delay at 60 MSPS tPD Full 6 ns Rise Time tR Full 1.9 ns Fall Time tF Full 1.2 ns Data Setup Time at 60 MSPS tDS Full 8.33 ns Data Hold Time at 60 MSPS tDH Full 6.0 ns Data Setup Time at 40 MSPS tDS Full 18 ns Data Hold Time at 40 MSPS tDH Full 6 ns Pipeline Latency Full 7 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology.
Timing and Switching Diagram N N –1 INAx tEH tEL CLK– CLK+ t t t PD DS DH D11 to D0 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
002 992- 10 Figure 2. Timing Definitions for Switching Specifications Rev. D | Page 6 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products
