Datasheet AD8284 (Analog Devices) - 8

AD8284 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DD33DRV DD33DRV NC DV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DV NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 48 NC PIN 1 SFLAG 2 47 TEST4 PDWN 3 46 DVDD18CLK DVDD18 4 45 CLK+ SCLK 5 44 CLK– CS 6 AD8284 43 DVDD33CLK SDI 7 TOP VIEW 42 AVDD33REF (Not to Scale) SDO 8 41 BAND AUX 9 40 VREF MUX[0] 10 39 RBIAS MUX[1] 11 38 APOUT ZSEL 12 37 ANOUT TEST1 13 36 TEST3 TEST2 14 35 AVDD18ADC DVDD33SPI 15 34 AGND NC 16 33 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC NC DD18 DD33 INA+ INA– INB+ INB– INC+ INC– IND+ IND– DD33 DD18 AV AV AV INADC+ INADC– AV NOTES
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1. TIE THE EXPOSED PAD ON THE BOTTOM SIDE TO THE ANALOG GROUND PLANE. 2. NC = NO CONNECTION. TIE NC TO ANY POTENTIAL.
10992- Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 NC No Connection. Tie NC to any potential. 2 SFLAG Saturation Flag. 3 PDWN Full Power-Down. A logic high on PDWN overrides the SPI and powers down the part; a logic low allows selection through the SPI. 4 DVDD18 1.8 V Digital Supply. 5 SCLK Serial Clock. 6 CS Chip Select. 7 SDI Serial Data Input. 8 SDO Serial Data Output. 9 AUX Auxiliary Channel. A logic high on AUX switches the AUX channel to ADC (INADC+/INADC−). 10 MUX[0] Digital Control for Mux Channel Selection. 11 MUX[1] Digital Control for Mux Channel Selection. 12 ZSEL Input Impedance Select. A logic high on ZSEL overrides the SPI and sets the input impedance to 200 kΩ; a logic low allows selection through the SPI. 13 TEST1 Test. Do not use the TEST1 pin; tie TEST1 to ground. 14 TEST2 Test. Do not use the TEST2 pin; tie TEST2 to ground. 15 DVDD33SPI 3.3 V Digital Supply, SPI Port. 16 NC No Connection. Tie NC to any potential. 17 NC No Connection. Tie NC to any potential. 18 AVDD18 1.8 V Analog Supply. 19 AVDD33 3.3 V Analog Supply. 20 INA+ Positive Mux Analog Input for Channel A. 21 INA− Negative Mux Analog Input for Channel A. 22 INB+ Positive Mux Analog Input for Channel B. 23 INB− Negative Mux Analog Input for Channel B. Rev. D | Page 8 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products