Datasheet AD9648-EP (Analog Devices) - 8

AD9648-EP Enhanced Product TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time 0.24 ns typ SSYNC t SYNC to rising edge of CLK+ hold time 0.40 ns typ HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns min DS t Hold time between the data and the rising edge of SCLK 2 ns min DH t Period of the SCLK 40 ns min CLK t Setup time between CSB and SCLK 2 ns min S t Hold time between CSB and SCLK 2 ns min H t SCLK pulse width high 10 ns min HIGH t SCLK pulse width low 10 ns min LOW t Time required for the SDIO pin to switch from an input to an output 10 ns min EN_SDIO relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an input 10 ns min DIS_SDIO relative to the SCLK rising edge
Timing Diagrams N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA N – 17 N – 16 N – 15 N – 14 N – 13 N – 12
002
tPD
13386- Figure 2. CMOS Default Output Mode Data Output Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A DATA N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 tPD
3 0
CH B CH A CH B CH A CH B CH A CH B CH A CH B
-0
CH B DATA N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
6 8 3 3 1 Figure 3. CMOS Interleaved Output Mode Data Output Timing Rev. B | Page 8 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE