Datasheet AD9286 (Analog Devices) - 10

AD9286 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DD 2– 2+ 1+ 1– N N DD DD EF DD M DD N N DD AV VI VI AV AV VR AV VC AV VI VI AV 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 36 AVDD PIN 1 AVDD 2 INDICATOR 35 AVDD AUXCLK+ 3 34 CLK+ AUXCLK– 4 33 CLK– RBIAS 5 32 CSB AD9286 AUXCLKEN 6 31 SDIO/PWDN DRGND 7 TOP VIEW 30 SCLK DRVDD 8 (Not to Scale) 29 OE D0– (LSB) 9 28 DRGND D0+ (LSB) 10 27 DRVDD D1– 11 26 D7+ (MSB) D1+ 12 25 D7– (MSB) 13 14 15 16 17 18 19 20 21 22 23 24 – + – + – + – + – + – + D2 D2 D3 D3 O D4 D4 D5 D5 D6 D6 DC DCO NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG
03 0
GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT
38-
DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
093 Figure 6. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description
ADC Power Pins 1, 2, 35, 36, 37, 40, 42, AVDD Supply Analog Power Supply (1.8 V Nominal). 44, 45, 48 8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 7, 28 DRGND Ground Digital Output Ground. 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ADC Analog Pins 39 VIN1+ Input Differential Analog Input Pin (+) for Channel 1. 38 VIN1− Input Differential Analog Input Pin (−) for Channel 1. 46 VIN2+ Input Differential Analog Input Pin (+) for Channel 2. 47 VIN2− Input Differential Analog Input Pin (−) for Channel 2. 43 VREF Input/output Voltage Reference Input/Output. 5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. 41 VCM Output Common-Mode Level Bias Output for Analog Inputs. 34 CLK+ Input ADC Clock Input—True. 33 CLK− Input ADC Clock Input—Complement. 3 AUXCLK+ Input Auxiliary ADC Clock Input—True. 4 AUXCLK− Input Auxiliary ADC Clock Input—Complement. Digital Inputs 6 AUXCLKEN Input Auxiliary Clock Input Enable. 29 OE Input Digital Enable (Active Low) to Tristate Output Data Pins. Digital Outputs 26 D7+ (MSB) Output Output Data 7—True. 25 D7− (MSB) Output Output Data 7—Complement. 24 D6+ Output Output Data 6—True. 23 D6− Output Output Data 6—Complement. 22 D5+ Output Output Data 5—True. 21 D5− Output Output Data 5—Complement. Rev. C | Page 10 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE