Datasheet AD9278 (Analog Devices)

Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator Data Sheet AD9278 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
The AD9278 is designed for low cost, low power, small size,
Low power: 88 mW per channel, TGC mode, 40 MSPS;
and ease of use for medical ultrasound and automotive radar. It
32 mW per channel, CW mode
contains eight channels of a variable gain amplifier (VGA) with
10 mm × 10 mm, 144-ball CSP-BGA
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
TGC channel input-referred noise: 1.3 nV/√Hz, max gain
analog-to-digital converter (ADC), and an I/Q demodulator
Flexible power-down modes
with programmable phase rotation.
Fast recovery from low power standby mode: <2 μs
Each channel features a variable gain range of 45 dB, a fully
Overload recovery: <10 ns
differential signal path, an active input preamplifier termination,
Low noise preamplifier (LNA)
and a maximum gain of up to 51 dB. The channel is optimized
Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
for high dynamic performance and low power in applications
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
where a smal package size is critical.
0.1 dB compression: 1000 mV p-p/ 750 mV p-p/450 mV p-p
The LNA has a single-ended-to-differential gain that is selectable
Dual-mode active input impedance matching
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
Bandwidth (BW): >50 MHz
and a 21.3 dB LNA gain, the LNA input SNR is roughly 88 dB.
Variable gain amplifier (VGA)
In CW Doppler mode, each LNA output drives an I/Q demod-
Attenuator range: −45 dB to 0 dB
ulator that has independently programmable phase rotation
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
with 16 phase settings.
Linear-in-dB gain control
Power-down of individual channels is supported to increase
Antialiasing filter (AAF)
battery life for portable applications. Standby mode al ows quick
Programmable second-order LPF from 8 MHz to 18 MHz
power-up for power cycling. In CW Doppler operation, the
Programmable HPF
VGA, AAF, and ADC are powered down. The ADC contains
Analog-to-digital converter (ADC)
several features designed to maximize flexibility and minimize
SNR: 70 dB, 12 bits up to 65 MSPS
system cost, such as a programmable clock, data alignment, and
Serial LVDS (ANSI-644, low power/reduced signal)
programmable digital test pattern generation. The digital test
CW mode I/Q demodulator
patterns include built-in fixed patterns, built-in pseudo random
Individual programmable phase rotation
patterns, and custom user-defined test patterns entered via the
Output dynamic range per channel: >158 dBc/√Hz
serial port interface.
Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3 dBFS FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 PDWN STBY DRVDD LO-A TO LO-H I/Q DEMODULATOR 8 CHANNELS LOSW-A TO LOSW-H LI-A TO LI-H 12-BIT SERIAL DOUTA+ TO DOUTH+ LNA VGA LG-A TO LG-H AAF ADC LVDS DOUTA– TO DOUTH– FCO+ SERIAL DATA LO FCO– REFERENCE PORT RATE GENERATION DCO+ INTERFACE MULTIPLIER DCO– ] – + I– I+ B K O N+ N– Q Q EF :3 AS K+ K– LO+ LO– DI
001
AI AI [0 CS CL ESET 4 4 CW CW S VR S CL CL G G CW CW RBI R PO
09424-
G
Figure 1.
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Document Outline Features General Description Functional Block Diagram Revision History Specifications AC Specifications Digital Specifications Switching Specifications ADC Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Equivalent Circuits Ultrasound Theory of Operation Channel Overview TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide