Datasheet AD9650-EP (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| Pages / Page | 12 / 4 — AD9650-EP. Data Sheet. ADC AC SPECIFICATIONS. Table 2. Parameter1. … |
| File Format / Size | PDF / 252 Kb |
| Document Language | English |
AD9650-EP. Data Sheet. ADC AC SPECIFICATIONS. Table 2. Parameter1. Temperature. Min. Typ. Max. Unit. DIGITAL SPECIFICATIONS
Model Line for this Datasheet
Text Version of Document
link to page 4 link to page 4
AD9650-EP Data Sheet ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 30 MHz 25°C 80.5 dBFS Full 78.4 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 30 MHz 25°C 80.2 dBFS Full 77.9 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 13 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −93 dBc Full −87 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 93 dBc Full 87 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz 25°C −101 dBc Full −94 dBc CROSSTALK2 Full −105 dBFS ANALOG INPUT BANDWIDTH 25°C 500 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled, unless otherwise noted.
Table 3. Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 µA Low Level Input Current Full −100 +100 µA Input Capacitance Full 9 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 µA Low Level Input Current Full −100 +100 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ Rev. 0 | Page 4 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
AD9650-EP Data Sheet ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 30 MHz 25°C 80.5 dBFS Full 78.4 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 30 MHz 25°C 80.2 dBFS Full 77.9 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 13 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −93 dBc Full −87 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 93 dBc Full 87 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz 25°C −101 dBc Full −94 dBc CROSSTALK2 Full −105 dBFS ANALOG INPUT BANDWIDTH 25°C 500 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled, unless otherwise noted.
Table 3. Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 µA Low Level Input Current Full −100 +100 µA Input Capacitance Full 9 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 µA Low Level Input Current Full −100 +100 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ Rev. 0 | Page 4 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
