Datasheet AD9650-EP (Analog Devices) - 9

Data Sheet AD9650-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS B SE A DD DD DD DD AS EF DD DD DD DD IN+ IN–B CM IN–A IN+ DNC DNC AV AV V V AV AV RBI V SEN VR AV AV V V AV AV DNC DNC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DNC 1 60 DNC PIN 1 DNC 2 IDENTIFIER 59 DNC CLK+ 3 58 PDWN CLK– 4 57 OEB SYNC 5 56 CSB D0– 6 55 SCLK/DFS D0+ 7 54 SDIO/DCS D1– 8 53 OR+ AD9650-EP D1+ 9 52 OR– TOP VIEW D2– 10 51 D15+ (Not to Scale) D2+ 11 50 CONNECT EXPOSED PAD TO GROUND D15– DRVDD 12 49 D14+ D3– 13 48 D14– D3+ 14 47 DRVDD D4– 15 46 D13+ D4+ 16 45 D13– D5– 17 44 D12+ D5+ 18 43 D12– DNC 19 42 DNC DNC 20 41 DNC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 – + DD DD DNC DNC D6– D6+ D7– D7+ D8– D8+ D9– D9+ DCO D10– D10+ DCO D11– D11+ DNC DNC DRV DRV NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
006
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
1312- 1 Figure 6. Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description
ADC Power Supplies 12, 25, 34, 47 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 63, 64, 67, 68, AVDD Supply Analog Power Supply (1.8 V Nominal). 73, 74, 77, 78 0 AGND, Ground The exposed thermal pad on the bottom of the package provides the analog ground Exposed Pad for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 65 VIN+A Input Differential Analog Input Pin (+) for Channel A. 66 VIN−A Input Differential Analog Input Pin (−) for Channel A. 76 VIN+B Input Differential Analog Input Pin (+) for Channel B. 75 VIN−B Input Differential Analog Input Pin (−) for Channel B. 69 VREF Input/output Voltage Reference Input/Output. 70 SENSE Input Voltage Reference Mode Select. 72 RBIAS Input/output External Reference Bias Resistor. 71 VCM Output Common-Mode Level Bias Output for Analog Inputs. 3 CLK+ Input ADC Clock Input—True. 4 CLK− Input ADC Clock Input—Complement. Digital Input 5 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 | Page 9 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide