Datasheet AD9266-EP (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 12 / 10 — AD9266-EP. Enhanced Product. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | B |
| File Format / Size | PDF / 241 Kb |
| Document Language | English |
AD9266-EP. Enhanced Product. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. N+I. N–I. RBI. SEN. CLK+ 1. 24 AVDD. CLK– 2. 23 MODE/OR. AVDD 3
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AD9266-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SE DD DD AS EF V N+I N–I V CM A V V A RBI V SEN VR 32 31 30 29 28 27 26 25 CLK+ 1 24 AVDD CLK– 2 23 MODE/OR AVDD 3 22 DCO CSB 4 AD9266-EP 21 (MSB) D15_D14 SCLK/DFS 5 TOP VIEW 20 D13_D12 (Not to Scale) SDIO/PDWN 6 19 D11_D10 DNC 7 18 D9_D8 DNC 8 17 D7_D6 9 1 10 1 12 13 14 15 16 DD B) DNC DNC DNC DNC V S R L D D3_D2 D5_D4 D1_D0 ( NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE DEVICE. IT MUST BE SOLDERED TO THE ANALOG
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GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY, HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH.
10476- Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and mechanical strength. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. 7 to 12 DNC Do Not Connect. 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 14 to 21 D1_D0 (LSB) to ADC Digital Outputs. (MSB) D15_D14 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 25 VREF 1.0 V Voltage Reference Input/Output. 26 SENSE Reference Mode Selection. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. B | Page 10 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
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GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY, HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH.
10476- Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and mechanical strength. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. 7 to 12 DNC Do Not Connect. 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 14 to 21 D1_D0 (LSB) to ADC Digital Outputs. (MSB) D15_D14 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 25 VREF 1.0 V Voltage Reference Input/Output. 26 SENSE Reference Mode Selection. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. B | Page 10 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
