Datasheet AD9276 (Analog Devices) - 8

link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8
AD9276 SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3. Parameter1 Temperature Min Typ Max Unit
CLOCK2 Clock Rate 40 MSPS (Mode I) Full 10 40 MHz 65 MSPS (Mode II) Full 10 65 MHz 80 MSPS (Mode III) Full 10 80 MHz Clock Pulse Width High (tEH) Full 6.25 ns Clock Pulse Width Low (tEL) Full 6.25 ns OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/24) ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Full ±100 ±350 ps Wake-Up Time (Standby), GAIN+ = 0.5 V 25°C 2 μs Wake-Up Time (Power-Down) 25°C 1 ms Pipeline Latency Full 8 Clock cycles APERTURE Aperture Uncertainty (Jitter) 25°C <1 ps rms LO GENERATION 4LO Frequency Full 4 40 MHz LO Divider RESET Setup Time5 Full 5 ns LO Divider RESET Hold Time5 Full 5 ns LO Divider RESET High Pulse Width Full 20 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 5 RESET edge to rising 4LO edge. Rev. 0 | Page 8 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE