Datasheet ADW12001 (Analog Devices) - 9

ADW12001 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS F T C ) E B L S D_RE M _A D D D _A N _A _A N D D K X_SE W B G V _A _A _A HARE 13_A ( 12_A 11_A 10_A AV CL S MU PD OE OTR D D D D DR DR D9 D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 D6_A VIN+_A 2 PIN 1 47 D5_A VIN–_A 3 46 D4_A AGND 4 45 D3_A AVDD 5 44 D2_A REFT_A 6 43 D1_A REFB_A 7 42 D0_A (LSB) ADW12001 VREF 8 TOP VIEW 41 DRVDD (Not to Scale) SENSE 9 40 DRGND REFB_B 10 39 OTR_B REFT_B 11 38 D13_B (MSB) AVDD 12 37 D12_B AGND 13 36 D11_B VIN–_B 14 35 D10_B VIN+_B 15 34 D9_B AGND 16 33 D8_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S ) D DD _B _B B _B _B _B _B _B _B _B K_B N DD DCS DF B S G V AV L D1 D2 D3 D4 D5 D6 D7 CL WN OE DR DR PD D0_B ( NOTES
3
1. THE ADW12001 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE
00 7-
OF THE PACKAGE THAT MUST BE CONNECTED TO PCB GND.
73 07 Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode. 20 DFS Data Output Format Select Pin. Low for offset binary, high for twos complement. 21 PDWN_B Power-Down Function Selection for Channel B. Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not high-Z). 22 OEB_B Output Enable Pin for Channel B. Logic 0 enables Data Bus B. Logic 1 sets outputs to high-Z. 23 to 27 D0_B (LSB) to D4_B Channel B Data Output Bits. 30 to 37 D5_B to D12_B Channel B Data Output Bits. 38 D13_B (MSB) Channel B Data Output Bits. 28, 40, 53 DRGND Digital Output Ground. Rev. 0 | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE