Datasheet AD9218-EP (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| Pages / Page | 11 / 7 — Enhanced Product. AD9218-EP. SAMPLE. N + 1. N + 2. N + 7. N + 8. AINA … |
| File Format / Size | PDF / 217 Kb |
| Document Language | English |
Enhanced Product. AD9218-EP. SAMPLE. N + 1. N + 2. N + 7. N + 8. AINA AINB. SAMPLE SAMPLE SAMPLE. N + 3. N + 4. N + 5. N + 6. tEH. 1/fS. ENCA. tPD. ENCB
Model Line for this Datasheet
Text Version of Document
Enhanced Product AD9218-EP SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCA tPD tV ENCB D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
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D9 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 B TO D0B
17309- Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCA tPD tV ENCB D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
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D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
17309- Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing Rev. 0 | Page 7 of 11 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
003
D9 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 B TO D0B
17309- Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCA tPD tV ENCB D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
004
D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
17309- Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing Rev. 0 | Page 7 of 11 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
