Datasheet ADRF6518 (Analog Devices) - 8

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ADRF6518 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE
VPS, VPI, VPSD = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, power mode bit (B9) = 0 (low power mode), digital gain code bits (B8 to B2) = 1111110, dc offset disable bit (B1) = 0 (enabled), filter corner = 63 MHz, ac coupling mode, fundamental at 31 MHz, unless otherwise noted. For HD2/HD3 vs. gain plots: 1.5 V p-p output target level, and reference Figure 67 for analog gain distribution.
0 4 –5 3 +25°C, VPS = 3.15V, 3.3V, 3.45V –10 2 –40°C, VPS = 3.15V, 3.3V, 3.45V –40°C, VPS = 3.15V, 3.3V, 3.45V –15 dB) 1 R ( dB) –20 N ( 0 RRO AI G N E –25 AI –1 G +25°C, VPS = 3.15V, 3.3V, 3.45V –30 –2 +85°C, VPS = 3.15V, 3.3V, 3.45V –35 –3 +85°C, VPS = 3.15V, 3.3V, 3.45V –40 –4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
005
0 100 200 300 400 500 600 700 800 900 1000
008
VGN1 (V) VGN1 (mV)
11449- 11449- Figure 5. In-Band Gain vs. VGN1 over Supply and Temperature Figure 8. Gain Error vs. VGN1 over Supply and Temperature
0 4 –5 3 +25°C, VPS = 3.15V, 3.3V, 3.45V –10 2 –40°C, VPS = 3.15V, 3.3V, 3.45V –40°C, VPS = 3.15V, 3.3V, 3.45V –15 dB) 1 dB) R ( –20 N ( 0 AI RRO G –25 N E AI –1 G +25°C, VPS = 3.15V, 3.3V, 3.45V –30 –2 +85°C, VPS = 3.15V, 3.3V, 3.45V –35 –3 +85°C, VPS = 3.15V, 3.3V, 3.45V –40 –4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
006
0 100 200 300 400 500 600 700 800 900 1000
009
VGN2 (V) VGN2 (mV)
11449- 11449- Figure 6. In-Band Gain vs. VGN2 over Supply and Temperature Figure 9. Gain Error vs. VGN2 over Supply and Temperature
0 4 –5 3 +25°C, VPS = 3.15V, 3.3V, 3.45V –10 2 –40°C, VPS = 3.15V, 3.3V, 3.45V –40°C, VPS = 3.15V, 3.3V, 3.45V –15 dB) 1 R ( dB) –20 N ( 0 RRO AI G N E –25 AI –1 G +25°C, VPS = 3.15V, 3.3V, 3.45V –30 –2 +85°C, VPS = 3.15V, 3.3V, 3.45V –35 –3 +85°C, VPS = 3.15V, 3.3V, 3.45V –40 –4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
007
0 100 200 300 400 500 600 700 800 900 1000
010
VGN3 (V) VGN3 (mV)
11449- 11449- Figure 7. In-Band Gain vs. VGN3 over Supply and Temperature Figure 10. Gain Error vs. VGN3 over Supply and Temperature Rev. A | Page 8 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE