Datasheet ADRF6516 (Analog Devices) - 3

Data Sheet ADRF6516 SPECIFICATIONS
VPS = 3.3 V, TA = 25°C, ZLOAD = 1 kΩ, digital gain code = 111, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RESPONSE Low-Pass Corner Frequency, fC 6-pole Butterworth filter, 0.5 dB bandwidth 1 31 MHz Step Size 1 MHz Corner Frequency Absolute Over operating temperature range ±15 % fC Accuracy Corner Frequency Matching Channel A and Channel B at same gain and ±0.5 % fC bandwidth settings Pass-Band Ripple 0.5 dB p-p Gain Matching Channel A and Channel B at same gain and ±0.1 dB bandwidth settings Group Delay Variation From midband to peak Corner Frequency = 1 MHz 135 ns Corner Frequency = 31 MHz 11 ns Group Delay Matching Channel A and Channel B at same gain Corner Frequency = 1 MHz 5 ns Corner Frequency = 31 MHz 0.2 ns Stop-Band Rejection Relative to Pass Band 2 × fC 30 dB 5 × fC 75 dB INPUT STAGE INP1, INM1, INP2, INM2, VICM pins Maximum Input Swing At minimum gain, VGAIN = 0 V 1 V p-p Differential Input Impedance 1600 Ω Input Common-Mode Range 0.4 V p-p input voltage, HD3 > 65 dBc 1.1 1.65 1.8 V Input pins left floating VPS/2 V VICM Output Impedance 7 kΩ GAIN CONTROL GAIN pin Voltage Gain Range VGAIN from 0 V to 1 V −5 +45 dB Gain Slope 15.5 mV/dB Gain Error VGAIN from 300 mV to 800 mV 0.2 dB OUTPUT STAGE OPP1, OPM1, OPP2, OPM2, VOCM pins Maximum Output Swing At maximum gain, RLOAD = 1 kΩ 2 V p-p HD2 > 65 dBc, HD3 > 65 dBc 1.5 V p-p Differential Output Impedance 30 Ω Output DC Offset Inputs shorted, offset loop disabled 35 mV Output Common-Mode Range 0.7 1.65 2.8 V VOCM pin left floating VPS/2 V VOCM Input Impedance 23 kΩ NOISE/DISTORTION Corner Frequency = 1 MHz Output Noise Density Gain = 0 dB at fC/2 −141 dBV/√Hz Gain = 20 dB at fC/2 −131 dBV/√Hz Gain = 40 dB at fC/2 −112 dBV/√Hz Second Harmonic, HD2 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 82 dBc Gain = 40 dB 68 dBc Third Harmonic, HD3 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 71 dBc Gain = 40 dB 56 dBc Rev. C | Page 3 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE