Datasheet ADRF6510 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 30 MHz Dual Programmable Filters and Variable Gain Amplifiers |
| Pages / Page | 32 / 4 — ADRF6510. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| Revision | B |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
ADRF6510. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
ADRF6510 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
IMD3 f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite output voltage Gain = 5 dB 61 dBc Gain = 35 dB 57 dBc IMD3 with Input CW Blocker f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite 40 dBc output, gain = 5 dB; blocker at 5 MHz, 10 dBc relative to two-tone composite output voltage 30 MHz Corner Frequency Output Noise Density Midband, gain = 0 dB −130 dBV/√Hz Midband, gain = 20 dB −130 dBV/√Hz Midband, gain = 40 dB −123 dBV/√Hz Second Harmonic, HD2 8 MHz fundamental, 1.5 V p-p output voltage Gain = 0 dB 63 dBc Gain = 40 dB 84 dBc Third Harmonic, HD3 8 MHz fundamental, 1.5 V p-p output voltage Gain = 0 dB 54 dBc Gain = 40 dB 87 dBc IMD3 f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite output voltage Gain = 5 dB 59 dBc Gain = 35 dB 77.5 dBc IMD3 with Input CW Blocker f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite 55 dBc output, gain = 5 dB; blocker at 150 MHz, 10 dBc relative to two-tone composite output voltage DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS, GNSW Input High Voltage, VINH >2 V Input Low Voltage, VINL <0.8 V Input Current, IINH/IINL <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO fCLK 1/tCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK to SDO delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL Supply Voltage Range 4.75 5.0 5.25 V Total Supply Current ENBL = 5 V Maximum bandwidth setting 258 mA Minimum bandwidth setting 131 mA Disable Current ENBL = 0 V 2 mA Disable Threshold 2.5 V Enable Response Time Delay following ENBL low-to-high transition 20 µs Disable Response Time Delay following ENBL high-to-low transition 300 ns Rev. B | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE
IMD3 f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite output voltage Gain = 5 dB 61 dBc Gain = 35 dB 57 dBc IMD3 with Input CW Blocker f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite 40 dBc output, gain = 5 dB; blocker at 5 MHz, 10 dBc relative to two-tone composite output voltage 30 MHz Corner Frequency Output Noise Density Midband, gain = 0 dB −130 dBV/√Hz Midband, gain = 20 dB −130 dBV/√Hz Midband, gain = 40 dB −123 dBV/√Hz Second Harmonic, HD2 8 MHz fundamental, 1.5 V p-p output voltage Gain = 0 dB 63 dBc Gain = 40 dB 84 dBc Third Harmonic, HD3 8 MHz fundamental, 1.5 V p-p output voltage Gain = 0 dB 54 dBc Gain = 40 dB 87 dBc IMD3 f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite output voltage Gain = 5 dB 59 dBc Gain = 35 dB 77.5 dBc IMD3 with Input CW Blocker f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite 55 dBc output, gain = 5 dB; blocker at 150 MHz, 10 dBc relative to two-tone composite output voltage DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS, GNSW Input High Voltage, VINH >2 V Input Low Voltage, VINL <0.8 V Input Current, IINH/IINL <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO fCLK 1/tCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK to SDO delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL Supply Voltage Range 4.75 5.0 5.25 V Total Supply Current ENBL = 5 V Maximum bandwidth setting 258 mA Minimum bandwidth setting 131 mA Disable Current ENBL = 0 V 2 mA Disable Threshold 2.5 V Enable Response Time Delay following ENBL low-to-high transition 20 µs Disable Response Time Delay following ENBL high-to-low transition 300 ns Rev. B | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE
